106 lines
3.9 KiB
C
106 lines
3.9 KiB
C
/** @file
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TCSS PEI PreMem policy
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2016 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _TCSS_PEI_PREMEM_CONFIG_H_
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#define _TCSS_PEI_PREMEM_CONFIG_H_
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#include <ConfigBlock.h>
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#define TCSS_PEI_PREMEM_CONFIG_REVISION 2
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extern EFI_GUID gTcssPeiPreMemConfigGuid;
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#pragma pack (push,1)
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///
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/// The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS.
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///
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typedef union {
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UINT32 TcssDevEn; ///< Maps to bits in TCSS_DEVEN_0_0_0_MCHBAR_IMPH
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struct{
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UINT32 TcssItbtPcie0En:1;
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UINT32 TcssItbtPcie1En:1;
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UINT32 TcssItbtPcie2En:1;
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UINT32 TcssItbtPcie3En:1;
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UINT32 :4;
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UINT32 TcssXhciEn:1;
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UINT32 TcssXdciEn:1;
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UINT32 TcssDma0En:1;
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UINT32 TcssDma1En:1;
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UINT32 :20;
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} TcssDevEnBit;
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} TCSS_DEVEN_PEI_PREMEM_CONFIG;
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///
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/// The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS.
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///
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typedef struct {
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UINT32 UsbTcPortEn : 4; ///< bitmap for USB Type C enabled ports
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UINT32 Rsvd : 28; ///< Reserved bytes for future use
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} TCSS_USBTC_PEI_PERMEM_CONFIG;
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/**
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The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS.\n
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<b>Revision 1</b>: - Initial version.
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**/
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typedef struct {
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/**
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This is policy to control Multiple Segment setting.
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When Disabled all the iTBT PCIe RP are located at Segment0
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When Enabled all the iTBT PCIe RP are located at Segment1,
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FSP Wrapper need to update PCIEXBAR and PcdPciExpressRegionLength to 512MB
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prior to FspmWrapperPeim.
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<b>0: Disable</b>, 1: Enable
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**/
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UINT8 PcieMultipleSegmentEnabled; /// Deprecate
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UINT8 Rsvd[3]; ///< Reserved bytes for future use, align to multiple 4
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} TCSS_MISC_PEI_PREMEM_CONFIG;
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/**
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This configuration block describes TCSS settings.\n
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Deprecate PcieMultipleSegmentEnabled
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
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TCSS_DEVEN_PEI_PREMEM_CONFIG DevEnConfig;///< TCSS DEVEN
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TCSS_USBTC_PEI_PERMEM_CONFIG UsbTcConfig;///< USB Type C Port Configuration
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TCSS_MISC_PEI_PREMEM_CONFIG MiscConfig; ///< The MISC PreMem Config
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} TCSS_PEI_PREMEM_CONFIG;
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#pragma pack (pop)
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#endif /* _TCSS_PEI_PREMEM_CONFIG_H_ */
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