133 lines
5.0 KiB
C
133 lines
5.0 KiB
C
/** @file
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Touch Host Controller policy.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2017 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _THC_CONFIG_H_
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#define _THC_CONFIG_H_
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#define THC_CONFIG_REVISION 3
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extern EFI_GUID gThcConfigGuid;
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#pragma pack (push,1)
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/**
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Available Port Assignments
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**/
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typedef enum {
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ThcAssignmentNone, ///< None of the avaialbe controllers assigned
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ThcAssignmentThc0, ///< Port assigned to THC0
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ThcAssignmentThc1 ///< Port assigned to THC1
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} THC_PORT_ASSIGNMENT;
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/**
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Available modes
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**/
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typedef enum {
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Thc, ///< Intel THC protocol
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HidOverSpi ///< Hid Over SPI protocol
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} THC_MODE;
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/**
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THC Hid Over SPI mode related settings. Only applicable when HidOverSpi is enbled.
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**/
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typedef struct {
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UINT32 ResetPad; ///< Reset Pad - <b>0x0 = THC HW default</b> BIOS will pass Pad infromation to ACPI, this Pad is used in _RST function or by the BIOS Quick SPI driver
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UINT32 ResetPadTrigger; ///< Reset Pad Trigger
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UINT32 Frequency; ///< Connection Speed - SPI Frequency in Hz
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UINT32 InputReportHeaderAddress; ///< Input Report Header Address
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UINT32 InputReportBodyAddress; ///< Input Report Body Address
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UINT32 OutputReportAddress; ///< Output Report Address
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UINT32 ReadOpcode; ///< Read Opcode
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UINT32 WriteOpcode; ///< Write Opcode
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UINT32 Flags; ///< Flags
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} THC_HID_OVER_SPI;
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/**
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Port Configuration structure required for each Port that THC might use.
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**/
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typedef struct {
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UINT32 Assignment; ///< Sets THCx assignment see THC_PORT_ASSIGNMENT
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UINT32 InterruptPinMuxing; ///< Each GPIO PORTx/SPIx INTB Pin has different muxing options refer to GPIO_*_MUXING_THC_SPIx_*
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UINT8 WakeOnTouch; ///< 1 = Enable <b>0 = Disable</b>. Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI
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UINT8 Mode; ///< 1 = Hid over SPI <b>0 = THC</b>. Switch between Intel THC protcol and Industry standard HID Over SPI protocol.
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UINT8 Reserved[2]; ///< Reserved
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THC_HID_OVER_SPI HidOverSpi; ///< Hid Over Spi mode settings
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UINT32 ActiveLtr; ///< <b>0xFFFFFFFF = Driver Default </b> Active Ltr
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UINT32 IdleLtr; ///< <b>0xFFFFFFFF = Driver Default </b> Idle Ltr
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UINT32 LimitPacketSize; ///< Limit Packet Size
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UINT32 PerformanceLimitation; ///< Performance Limitation
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} THC_PORT;
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/**
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THC_CONFIG block provides the configurations forTouch Host Controllers
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Assignment field in each THC port controlls the THC behavior.
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Available scenarios:
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1: Single Port 0 used by THC0
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- THC0 Enabled
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- Port0 assigned to THC0
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- Port1 unassigned
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- THC1 will be automatically Disabled.
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2: Both ports used by THC0
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- THC0 Enabled
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- Port0 assigned to THC0
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- Port1 assigned to THC0
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- THC1 will be automatically Disabled.
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3: Port 0 used by THC0 and Port 1 used by THC1
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- THC0 Enabled
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- Port0 assigned to THC0
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- THC1 Enabled
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- Port1 assigned to THC1.
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<b>4: Both Ports unassigned.</b>
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Both THC Controllers will be disabled in that case.
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@note
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Invalid scenario that will cause ASSERT.
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1. Same port Number assigned to THC0 or THC1.
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2. Two Ports assigned to THC1.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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THC_PORT ThcPort[2]; ///< Port Configuration
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} THC_CONFIG;
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#pragma pack (pop)
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#endif // _THC_CONFIG_H_
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