182 lines
7.4 KiB
C
182 lines
7.4 KiB
C
/** @file
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Thermal policy
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2018 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _THERMAL_CONFIG_H_
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#define _THERMAL_CONFIG_H_
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#define THERMAL_CONFIG_REVISION 1
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extern EFI_GUID gThermalConfigGuid;
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#pragma pack (push,1)
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/**
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This structure lists PCH supported throttling register setting for custimization.
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When the SuggestedSetting is enabled, the customized values are ignored.
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**/
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typedef struct {
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UINT32 T0Level : 9; ///< Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
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UINT32 T1Level : 9; ///< Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
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UINT32 T2Level : 9; ///< Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
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UINT32 TTEnable : 1; ///< Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
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/**
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When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.
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If SuggestedSetting is used, this setting is ignored.
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**/
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UINT32 TTState13Enable : 1;
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/**
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When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.
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If SuggestedSetting is used, this setting is ignored.
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**/
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UINT32 TTLock : 1;
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UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values.
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/**
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ULT processors support thermal management and cross thermal throttling between the processor package
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and LP PCH. The PMSYNC message from PCH to CPU includes specific bit fields to update the PCH
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thermal status to the processor which is factored into the processor throttling.
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Enable/Disable PCH Cross Throttling; 0: Disabled, 1: <b>Enabled</b>.
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**/
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UINT32 PchCrossThrottling : 1;
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UINT32 Rsvd0; ///< Reserved bytes
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} THERMAL_THROTTLE_LEVELS;
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//
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// Supported Thermal Sensor Target Width
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//
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typedef enum {
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DmiThermSensWidthX1 = 0,
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DmiThermSensWidthX2 = 1,
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DmiThermSensWidthX4 = 2,
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DmiThermSensWidthX8 = 3,
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DmiThermSensWidthX16 = 4
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} DMI_THERMAL_SENSOR_TARGET_WIDTH;
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/**
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This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design.
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When the SuggestedSetting is enabled, the customized values are ignored.
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Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values
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**/
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typedef struct {
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UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous Width Enable
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UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
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UINT32 RsvdBits0 : 6; ///< Reserved bits
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UINT32 TS0TW : 3; ///< Thermal Sensor 0 Target Width (<b>DmiThermSensWidthx8</b>)
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UINT32 TS1TW : 3; ///< Thermal Sensor 1 Target Width (<b>DmiThermSensWidthx4</b>)
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UINT32 TS2TW : 3; ///< Thermal Sensor 2 Target Width (<b>DmiThermSensWidthx2</b>)
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UINT32 TS3TW : 3; ///< Thermal Sensor 3 Target Width (<b>DmiThermSensWidthx1</b>)
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UINT32 RsvdBits1 : 12; ///< Reserved bits
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} DMI_HW_WIDTH_CONTROL;
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/**
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This structure configures PCH memory throttling thermal sensor GPIO PIN settings
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**/
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typedef struct {
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/**
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GPIO PM_SYNC enable, 0:Diabled, 1:<b>Enabled</b>
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When enabled, RC will overrides the selected GPIO native mode.
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For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1
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For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2
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For CNL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, CPU_GP_3 is GPP_B4.
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**/
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UINT32 PmsyncEnable : 1;
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UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 state, 0:Disabled, 1:<b>Enabled</b>
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UINT32 PinSelection : 1; ///< GPIO Pin assignment selection, <b>0: default</b>, 1: secondary
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UINT32 RsvdBits0 : 29;
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} TS_GPIO_PIN_SETTING;
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enum PCH_PMSYNC_GPIO_X_SELECTION {
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TsGpioC,
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TsGpioD,
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MaxTsGpioPin
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};
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/**
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This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board).
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**/
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typedef struct {
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/**
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This will enable PCH memory throttling.
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While this policy is enabled, must also enable EnableExtts in SA policy.
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<b>0: Disable</b>; 1: Enable
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**/
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UINT32 Enable : 1;
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UINT32 RsvdBits0 : 31;
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/**
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GPIO_C and GPIO_D selection for memory throttling.
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It's strongly recommended to choose GPIO_C and GPIO_D for memory throttling feature,
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and route EXTTS# accordingly.
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**/
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TS_GPIO_PIN_SETTING TsGpioPinSetting[2];
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} PCH_MEMORY_THROTTLING;
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/**
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The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 PchHotEnable : 1; ///< Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: <b>Disabled<b>, 1: Enabled.
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UINT32 RsvdBits0 : 31;
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/**
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This field decides the settings of Thermal throttling. When the Suggested Setting
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is enabled, PCH RC will use the suggested representative values.
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**/
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THERMAL_THROTTLE_LEVELS TTLevels;
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/**
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This field decides the settings of DMI throttling. When the Suggested Setting
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is enabled, PCH RC will use the suggested representative values.
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**/
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DMI_HW_WIDTH_CONTROL DmiHaAWC;
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/**
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Memory Thermal Management settings
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**/
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PCH_MEMORY_THROTTLING MemoryThrottling;
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/**
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The recommendation is the same as Cat Trip point.
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This field decides the temperature, default is <b>120</b>.
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Temperature value used for PCHHOT# pin assertion based on 2s complement format
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- 0x001 positive 1'C
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- 0x000 0'C
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- 0x1FF negative 1'C
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- 0x1D8 negative 40'C
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- and so on
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**/
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UINT16 PchHotLevel;
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UINT8 Rsvd0[6];
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} THERMAL_CONFIG;
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#pragma pack (pop)
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#endif // _THERMAL_CONFIG_H_
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