189 lines
7.8 KiB
C
189 lines
7.8 KiB
C
/** @file
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Common USB policy shared between PCH and CPU
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Contains general features settings for xHCI and xDCI
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2017 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _USB_CONFIG_H_
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#define _USB_CONFIG_H_
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#define USB_CONFIG_REVISION 3
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extern EFI_GUID gUsbConfigGuid;
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#define MAX_USB2_PORTS 16
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#define MAX_USB3_PORTS 10
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#pragma pack (push,1)
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typedef UINT8 USB_OVERCURRENT_PIN;
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#define USB_OC_SKIP 0xFF
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#define USB_OC_MAX_PINS 16 ///< Total OC pins number (both physical and virtual)
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/**
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This structure configures per USB2.0 port settings like enabling and overcurrent protection
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**/
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typedef struct {
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/**
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These members describe the specific over current pin number of USB 2.0 Port N.
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It is SW's responsibility to ensure that a given port's bit map is set only for
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one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.
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**/
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UINT32 OverCurrentPin : 8;
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UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
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UINT32 PortResetMessageEnable : 1; ///< 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
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UINT32 RsvdBits0 : 22; ///< Reserved bits
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} USB2_PORT_CONFIG;
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/**
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This structure configures per USB3.x port settings like enabling and overcurrent protection
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**/
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typedef struct {
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/**
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These members describe the specific over current pin number of USB 3.x Port N.
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It is SW's responsibility to ensure that a given port's bit map is set only for
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one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.
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**/
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UINT32 OverCurrentPin : 8;
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UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
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UINT32 RsvdBits0 : 23; ///< Reserved bits
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} USB3_PORT_CONFIG;
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/**
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The XDCI_CONFIG block describes the configurations
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of the xDCI Usb Device controller.
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**/
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typedef struct {
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/**
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This member describes whether or not the xDCI controller should be enabled.
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0: Disable; <b>1: Enable</b>.
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**/
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UINT32 Enable : 1;
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UINT32 RsvdBits0 : 31; ///< Reserved bits
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} XDCI_CONFIG;
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/**
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This member describes the expected configuration of the USB controller,
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Platform modules may need to refer Setup options, schematic, BIOS specification to update this field.
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The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated by referring the schematic.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Added UaolEnable to control USB Audio Offload Capability.
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<b>Revision 3</b>:
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- Add HsiiEnable enable option to control HSII feature
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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This policy option when set will make BIOS program Port Disable Override register during PEI phase.
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When disabled BIOS will not program the PDO during PEI phase and leave PDO register unlocked for later programming.
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If this is disabled, platform code MUST set it before booting into OS.
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<b>1: Enable</b>
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0: Disable
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**/
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UINT32 PdoProgramming : 1;
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/**
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This option allows for control whether USB should program the Overcurrent Pins mapping into xHCI.
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Disabling this feature will disable overcurrent detection functionality.
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Overcurrent Pin mapping data is contained in respective port structures (i.e. USB30_PORT_CONFIG) in OverCurrentPin field.
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By default this Overcurrent functionality should be enabled and disabled only for OBS debug usage.
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<b>1: Will program USB OC pin mapping in respective xHCI controller registers</b>
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0: Will clear OC pin mapping allow for OBS usage of OC pins
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**/
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UINT32 OverCurrentEnable : 1;
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/**
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<b>(Test)</b>
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If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be
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consumed by xHCI and OC mapping registers will be locked. OverCurrent mapping data is taken from respective port data
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structure from OverCurrentPin field.
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If EnableOverCurrent policy is enabled this also should be enabled, otherwise xHCI won't consume OC mapping data.
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<b>1: Program OCCFDONE bit and make xHCI consume OverCurrent mapping data</b>
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0: Do not program OCCFDONE bit making it possible to use OBS debug on OC pins.
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**/
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UINT32 XhciOcLock : 1;
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/**
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Enabling this feature will allow for overriding LTR values for xHCI controller.
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Values used for programming will be taken from this config block and BIOS will disregard recommended ones.
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<b>0: disable - do not override recommended LTR values</b>
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1: enable - override recommended LTR values
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**/
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UINT32 LtrOverrideEnable : 1;
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/**
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Enable/disable option for USB Audio Offload feture. Disabling this will disable UAOL capability
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in xHCI and UAOL ACPI definitions will be hidden.
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0: disable UAOL
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<b>1: enable UAOL</b>
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**/
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UINT32 UaolEnable : 1;
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/**
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Enable HS Interrupt IN Alarm
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0: disable - Disable HSII
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<b>1: enable - Enable HSII</b>
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**/
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UINT32 HsiiEnable : 1;
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UINT32 RsvdBits0 : 26; ///< Reserved bits
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/**
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High Idle Time Control override value
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This setting is used only if LtrOverrideEnable is enabled
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**/
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UINT32 LtrHighIdleTimeOverride;
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/**
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Medium Idle Time Control override value
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This setting is used only if LtrOverrideEnable is enabled
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**/
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UINT32 LtrMediumIdleTimeOverride;
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/**
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Low Idle Time Control override value
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This setting is used only if LtrOverrideEnable is enabled
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**/
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UINT32 LtrLowIdleTimeOverride;
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/**
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These members describe whether the USB2 Port N of PCH is enabled by platform modules.
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**/
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USB2_PORT_CONFIG PortUsb20[MAX_USB2_PORTS];
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/**
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These members describe whether the USB3 Port N of PCH is enabled by platform modules.
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**/
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USB3_PORT_CONFIG PortUsb30[MAX_USB3_PORTS];
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/**
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This member describes whether or not the xDCI controller should be enabled.
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**/
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XDCI_CONFIG XdciConfig;
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} USB_CONFIG;
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#pragma pack (pop)
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#endif // _USB_CONFIG_H_
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