76 lines
4.3 KiB
C
76 lines
4.3 KiB
C
/** @file
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The GUID definition for CpuPcieHob
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _CPU_PCIE_HOB_H_
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#define _CPU_PCIE_HOB_H_
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#include <Base.h>
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#include <CpuPcieInfo.h>
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#include <CpuPcieConfig.h>
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extern EFI_GUID gCpuPcieHobGuid;
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#pragma pack (push,1)
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/**
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The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers
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**/
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typedef struct {
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///
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/// These members describe the configuration of each CPU PCIe root port.
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///
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EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gCpuPcieHobGuid
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CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
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UINT8 L1SubStates[CPU_PCIE_MAX_ROOT_PORTS]; ///< The L1 Substates configuration of the root port
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UINT32 DekelFwVersionMinor; ///< Dekel Firmware Minor Version
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UINT32 DekelFwVersionMajor; ///< Dekel Firmware Major Version
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BOOLEAN InitPcieAspmAfterOprom; ///< 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
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UINT32 RpEnabledMask; ///< Rootport enabled mask based on DEVEN register
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UINT32 RpEnMaskFromDevEn; ///< Rootport enabled mask based on Device Id
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UINT8 DisableClkReqMsg[CPU_PCIE_MAX_ROOT_PORTS]; ///< 1=ClkReqMsg disabled, 0=ClkReqMsg enabled
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UINT8 SlotSelection; ///< 1=M2 slot, 0=CEMx4 slot
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BOOLEAN ComplianceTest; ///< Compliance Test based on policy
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UINT32 HsPhyRecipeVersionMajor; ///< HS-Phy Recipe Major Version
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UINT32 HsPhyRecipeVersionMinor; ///< HS-Phy Recipe Minor Version
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UINT32 HsPhyFwProdMajor; ///< HS-Phy Firmware Product Major Verison
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UINT32 HsPhyFwProdMinor; ///< HS-Phy Firmware Product Minor Verison
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UINT32 HsPhyFwHotFix; ///< HS-Phy Firmware Hot Fix Version
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UINT32 HsPhyFwBuild; ///< HS-Phy Firmware Build version
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UINT32 HsPhyFwEvBitProgMajor; ///< HS-Phy Firmware EV Bit Prog Major
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UINT32 HsPhyFwEvBitProgMinor; ///< HS-Phy Firmware EV Bit Prog Minor
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UINT32 HsPhyMap; ///< HS-Phy Mapping Based on HS-Py supported ports
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} CPU_PCIE_HOB;
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#pragma pack (pop)
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#endif
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