70 lines
3.5 KiB
C
70 lines
3.5 KiB
C
/** @file
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The GUID definition for CpuPcieHob
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2019 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _CPU_PCIE_HOB_GEN3_H_
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#define _CPU_PCIE_HOB_GEN3_H_
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#include <Base.h>
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#include <CpuPcieInfo.h>
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#include <CpuPcieConfigGen3.h>
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extern EFI_GUID gSaPegHobGuid;
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#pragma pack (push,1)
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/**
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PEG data definition
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This structure can be saved in non-volatile memory to be re-used in the following boot.
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By this way reference code will not re-do PCIe Preset Search and save POST time
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SI_POLICY_PPI can be used to pass the pointer of pre-saved SA_PEG_DATA by platform code
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**/
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typedef struct {
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UINT32 EndPointVendorIdDeviceId[SA_PEG_MAX_FUN_GEN3]; ///< Offset 0 - 11: VID/DID for each PEG controller
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UINT8 BestPreset[SA_PEG_MAX_LANE_GEN3]; ///< Offset 12 - 27: Best preset value for each lane
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UINT8 PegGen3PresetSearch; ///< Offset 28: Preset search value
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UINT8 PegLinkFailMask; ///< Offset 29: Mask of PEG controllers to ignore
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UINT8 Rsvd0[2]; ///< Offset 30: Reserved for future use.
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} SA_PEG_DATA;
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///
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/// System Agent PEG NVS Hob
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///
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typedef struct {
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EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gSaPegHobGuid
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BOOLEAN InitPcieAspmAfterOprom; ///< 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
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SA_PEG_DATA PegData; ///< Offset 24 (Move to FSP NVS Hob) PEG data definition
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UINT8 PowerDownUnusedBundles[SA_PEG_MAX_FUN_GEN3]; ///< PCIe power down unused bundles support
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BOOLEAN PegPlatformResetRequired; ///< 1=platform code should generate a cold/power cycle reset after saving PEG config data into NVRAM
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} SA_PEG_HOB;
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#pragma pack (pop)
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#endif
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