76 lines
2.7 KiB
C
76 lines
2.7 KiB
C
/** @file
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Definitions required to create PcieStorageInfoHob
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2016 - 2019 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _PCH_PCIE_STORAGE_DETECT_HOB_
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#define _PCH_PCIE_STORAGE_DETECT_HOB_
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#include "PchLimits.h"
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#define PCIE_STORAGE_INFO_HOB_REVISION 1
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extern EFI_GUID gPchPcieStorageDetectHobGuid;
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typedef enum {
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RstLinkWidthX1 = 1,
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RstLinkWidthX2 = 2,
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RstLinkWidthX4 = 4
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} RST_LINK_WIDTH;
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//
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// Stores information about connected PCIe storage devices used later by BIOS setup and RST remapping
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//
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#pragma pack(1)
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typedef struct {
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UINT8 Revision;
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//
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// Stores the number of root ports occupied by a connected storage device, values from RST_LINK_WIDTH are supported
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//
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UINT8 PcieStorageLinkWidth[PCH_MAX_PCIE_ROOT_PORTS];
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//
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// Programming interface value for a given device, 0x02 - NVMe or RAID, 0x1 - AHCI storage, 0x0 - no device connected
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//
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UINT8 PcieStorageProgrammingInterface[PCH_MAX_PCIE_ROOT_PORTS];
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//
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// Stores information about cycle router number under a given PCIe controller
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//
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UINT8 RstCycleRouterMap[PCH_MAX_PCIE_CONTROLLERS];
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} PCIE_STORAGE_INFO_HOB;
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#pragma pack()
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#endif
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