81 lines
3.5 KiB
C
81 lines
3.5 KiB
C
/** @file
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ITBT Policy definition to be referred in both PEI and DXE phase.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2017 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _ITBT_POLICY_GENERIC_H_
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#define _ITBT_POLICY_GENERIC_H_
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#pragma pack(push, 1)
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///
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/// iTBT RootPort Data Structure
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///
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typedef struct _ITBT_ROOTPORT_CONFIG{
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UINT8 ITbtPcieRootPortEn; ///< Disable/Enable iTBT PCIe Root Port
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UINT8 Reserved[3]; ///< Reserved for DWORD alignment
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} ITBT_ROOTPORT_CONFIG;
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///
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/// ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB
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///
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typedef struct _ITBT_GENERIC_CONFIG{
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/**
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Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for execution of following
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mailbox communication.
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After applying Force Power Thunderbolt BIOS shall poll for iTBT readiness for mailbox communication
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If TBT cable is disconnected, iTBT microcontrollers are in lower power state.
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To ensure successful mailbox execution, independently on presence of TBT cable, TBT BIOS shall bring iTBT
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microcontrollers up by applying Force Power. iTBT microcontrollers will wake up either due to TBT cable presence or
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Force Power event.
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<b>(Test)</b>
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<b> default is 500 ms </b>
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**/
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UINT16 ITbtForcePowerOnTimeoutInMs;
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/**
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Timeout value while sending connect topology mailbox command in order to bring all connected TBT devices are available
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on PCIe before BIOS will enumerate them in BDS
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<b>(Test)</b>
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<b> default is 5000 ms </b>
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**/
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UINT16 ITbtConnectTopologyTimeoutInMs;
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UINT8 ITbtSecurityLevel; ///< iTbt Security Level <b>Deprecated</b>
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UINT8 ITbtPcieTunnelingForUsb4; ///< Disable/Enable PCIe tunneling for USB4. <b>default is enable</b>
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UINT8 Usb4CmMode; ///< USB4 CM mode
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UINT8 Reserved[1]; ///< Reserved for DWORD alignment
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} ITBT_GENERIC_CONFIG;
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#pragma pack(pop)
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#endif
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