156 lines
3.8 KiB
C
156 lines
3.8 KiB
C
/** @file
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PEI SA Init FRU Lib header file
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _PEI_SA_INIT_FRU_LIB_H_
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#define _PEI_SA_INIT_FRU_LIB_H_
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#include <Ppi/SiPolicy.h>
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#include <SaConfigHob.h>
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#include <Library/BaseLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <CpuPcieHobGen3.h>
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#include <Library/IoLib.h>
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#include <Base.h>
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#include <Library/PeiHostBridgeInitLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/ConfigBlockLib.h>
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#include <Library/CpuDmiInfoLib.h>
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#include <Register/GnaRegs.h>
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#include <Library/GnaInitLib.h>
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#include <Library/PostCodeLib.h>
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#include <Library/DebugLib.h>
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//
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// Functions
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//
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/**
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Programs WRC (Write Cache) Feature for IOP.
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@param[in] MiscPeiPreMemConfig - Instance of SA_MISC_PEI_PREMEM_CONFIG
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**/
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VOID
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ProgramWrcFeatureForIop (
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IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig
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);
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/**
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Init and Install CPU Pcie Gen3 Hob
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@param[out] SaPegHob - SA_PEG_HOB instance installed by this function
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@retval EFI_SUCCESS
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**/
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EFI_STATUS
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InstallCpuPcieGen3Hob (
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OUT SA_PEG_HOB **SaPegHobOut
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);
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/**
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This function performs SA internal devices enabling/disabling
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@param[in] HostBridgePeiConfig - Instance of HOST_BRIDGE_PEI_CONFIG
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@param[in] GnaConfig - Instance of GNA_CONFIG
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**/
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VOID
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DeviceConfigure(
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IN HOST_BRIDGE_PEI_CONFIG *HostBridgePeiConfig,
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IN GNA_CONFIG *GnaConfig
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);
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/**
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This function does SA security lock
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**/
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VOID
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SaSecurityLock(
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VOID
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);
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/**
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Program Host Bridge work arounds
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**/
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VOID
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HostBridgeWorkAround(
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VOID
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);
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/**
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Update SA Hob in PostMem
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@param[in] GtConfig - Instance of GRAPHICS_PEI_PREMEM_CONFIG
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@retval EFI_SUCCESS
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**/
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EFI_STATUS
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UpdateSaHobPostMem (
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IN GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig
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);
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/**
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Get the GFX revision and update the same in ScratchPad register
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**/
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VOID
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UpdateGfxRevisionToScratchpad (
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VOID
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);
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/**
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Disable Gna Device
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**/
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VOID
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DisableGnaDevice (
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VOID
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);
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/**
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Enable Gna Device
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**/
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VOID
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EnableGnaDevice (
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VOID
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);
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/**
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This function loads MemConfigSaGv default values
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@param[in] MemConfig Pointer to Memory Config block
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**/
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VOID
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UpdateMemConfigSaGvDefault(
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IN MEMORY_CONFIGURATION *MemConfig
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);
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#endif
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