276 lines
8.4 KiB
Plaintext
276 lines
8.4 KiB
Plaintext
/** @file
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This file contains the system BIOS call back functionality for the
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OpRegion/Software SCI mechanism.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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Method (SBCB, 0, Serialized)
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{
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//
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// Supported Callbacks: Sub-function 0
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//
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If (LEqual(GESF, 0x0))
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{
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//
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//<NOTE> An OEM may support the driver->SBIOS status callbacks, but
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// the supported callbacks value must be modified. The code that is
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// executed upon reception of the callbacks must be also be updated
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// to perform the desired functionality.
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//
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Store(0x00000000, PARM) // No callbacks supported
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//Store(0x000787FD, PARM) // Used for Intel test implementaion
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Store(0x000F87DD, PARM)
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Store(Zero, GESF) // Clear the exit parameter
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Return(SUCC) // "Success"
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}
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//
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// BIOS POST Completion: Sub-function 1
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//
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If (LEqual(GESF, 1))
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{
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Not supported, but no failure
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}
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//
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// Pre-Hires Set Mode: Sub-function 3
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//
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If (LEqual(GESF, 3))
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{
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Not supported, but no failure
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}
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//
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// Post-Hires Set Mode: Sub-function 4
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//
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If (LEqual(GESF, 4))
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{
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Not supported, but no failure
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}
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//
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// Display Switch: Sub-function 5
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//
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If (LEqual(GESF, 5))
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{
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Not supported, but no failure
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}
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//
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// Adapter Power State: Sub-function 7
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//
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If (LEqual(GESF, 7))
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{
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//
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// Handle Low Power S0 Idle Capability if enabled
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//
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If(LAnd(LEqual(S0ID, 1),LLess(OSYS, 2015))) {
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//
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// Call GUAM to trigger CS Entry
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// If Adapter Power State Notification = D1 (PARM[7:0]=0x01)
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//
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If (LEqual (And(PARM,0xFF), 0x01)) {
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// GUAM - Global User Absent Mode Notification Method
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\GUAM(One) // 0x01 - Power State Standby (CS Entry)
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}
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If (LEqual (And(PARM,0xFF), 0x00)) {
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// GUAM - Global User Absent Mode Notification Method
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\GUAM(0)
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}
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}
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//
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// Upon notification from driver that the Adapter Power State = D0,
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// check if previous lid event failed. If it did, retry the lid
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// event here.
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//
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If(LEqual(PARM, 0))
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{
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Store(CLID, Local0)
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If(And(0x80000000,Local0))
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{
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And(CLID, 0x0000000F, CLID)
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GLID(CLID)
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}
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}
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Not supported, but no failure
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}
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//
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// Display Power State: Sub-function 8
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//
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If (LEqual(GESF, 8))
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{
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Not supported, but no failure
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}
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//
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// Set Boot Display: Sub-function 9
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//
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If (LEqual(GESF, 9))
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{
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//
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//<NOTE> An OEM may elect to implement this method. In that case,
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// the input values must be saved into non-volatile storage for
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// parsing during the next boot. The following Sample code is Intel
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// validated implementation.
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//
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And(PARM, 0xFF, IBTT) // Save the boot display to NVS
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Reserved, "Critical failure"
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}
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//
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// Set Panel Details: Sub-function 10 (0Ah)
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//
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If (LEqual(GESF, 10))
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{
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//
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//<NOTE> An OEM may elect to implement this method. In that case,
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// the input values must be saved into non-volatile storage for
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// parsing during the next boot. The following Sample code is Intel
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// validated implementation.
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// Set the panel-related NVRAM variables based the input from the driver.
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//
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And(PARM, 0xFF, IPSC)
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//
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// Change panel type if a change is requested by the driver (Change if
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// panel type input is non-zero). Zero=No change requested.
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//
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If(And(ShiftRight(PARM, 8), 0xFF))
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{
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And(ShiftRight(PARM, 8), 0xFF, IPAT)
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Decrement(IPAT) // 0 = no change, so fit to CMOS map
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}
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And(ShiftRight(PARM, 20), 0x7, IBIA)
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Success
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}
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//
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// Set Internal Graphics: Sub-function 11 (0Bh)
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//
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If (LEqual(GESF, 11))
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{
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//
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//<NOTE> An OEM may elect to implement this method. In that case,
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// the input values must be saved into non-volatile storage for
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// parsing during the next boot. The following Sample code is Intel
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// validated implementation.
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//
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And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 option
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Success
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}
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//
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// Post-Hires to DOS FS: Sub-function 16 (10h)
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//
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If (LEqual(GESF, 16))
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{
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Not supported, but no failure
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}
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//
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// APM Complete: Sub-function 17 (11h)
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//
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If (LEqual(GESF, 17))
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{
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Store(ShiftLeft(LIDS, 8), PARM) // Report the lid state
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Add(PARM, 0x100, PARM) // Adjust the lid state, 0 = Unknown
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Store(Zero, GESF) // Clear the exit parameter
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Return(SUCC) // Not supported, but no failure
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}
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//
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// Set Spread Spectrum Clocks: Sub-function 18 (12h)
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//
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If (LEqual(GESF, 18))
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{
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//
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//<NOTE> An OEM may elect to implement this method. In that case,
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// the input values must be saved into non-volatile storage for
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// parsing during the next boot. The following Sample code is Intel
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// validated implementation.
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//
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If(And(PARM, 1))
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{
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If(LEqual(ShiftRight(PARM, 1), 1))
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{
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Store(1, ISSC) // Enable HW SSC, only for clock 1
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}
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Else
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{
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Store(Zero, GESF)
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Return(CRIT) // Failure, as the SSC clock must be 1
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}
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}
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Else
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{
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Store(0, ISSC) // Disable SSC
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}
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Success
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}
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//
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// Post VBE/PM Callback: Sub-function 19 (13h)
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//
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If (LEqual(GESF, 19))
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{
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Not supported, but no failure
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}
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//
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// Set PAVP Data: Sub-function 20 (14h)
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//
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If (LEqual(GESF, 20))
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{
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And(PARM, 0xF, PAVP) // Store PAVP info
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Store(Zero, GESF) // Clear the exit parameter
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Store(Zero, PARM)
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Return(SUCC) // Success
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}
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//
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// A call to a reserved "System BIOS callbacks" function was received
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//
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Store(Zero, GESF) // Clear the exit parameter
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Return(SUCC) // Reserved, "Critical failure"
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}
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