95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
/** @file
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PMC SoC configuration
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _PMC_SOC_CONFIGURATION_H_
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#define _PMC_SOC_CONFIGURATION_H_
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typedef enum {
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AdrSinglePhase = 0,
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AdrDualPhase
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} ADR_PHASE_TYPE;
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typedef enum {
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AdrGpioB = 0,
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AdrGpioC
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} ADR_GPIO;
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typedef enum {
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AdrOverPmSync = 0,
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AdrOverDmi
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} ADR_MSG_INTERFACE;
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typedef struct {
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BOOLEAN Supported;
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ADR_PHASE_TYPE AdrPhaseType;
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ADR_GPIO AdrGpio;
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ADR_MSG_INTERFACE AdrMsgInterface;
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//
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// On some designs ADR_GEN_CFG has been moved in the HW.
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// Set this to if ADR_GEN_CFG is located at 0x1908
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//
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BOOLEAN AdrGenCfgMoved;
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} PMC_ADR_SOC_CONFIG;
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typedef struct {
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BOOLEAN CppmCgInterfaceVersion;
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BOOLEAN LpmSupported;
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UINT8 LpmInterfaceVersion;
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BOOLEAN OsIdleSupported;
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BOOLEAN TimedGpioSupported;
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UINT32 CpuIovrRampTime;
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BOOLEAN PsOnSupported;
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BOOLEAN ModPhySusPgSupported;
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UINT8 SciIrq;
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BOOLEAN FabricPowerGatingCppmQualificationEnable;
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BOOLEAN EspiBoot;
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BOOLEAN UsbDbcConnected;
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UINT32 Usb3LanesConnectedBitmask;
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BOOLEAN DisableIosfSbClockGating;
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BOOLEAN SkipModPhyGatingPolicy;
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PMC_ADR_SOC_CONFIG AdrSocConfig;
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BOOLEAN AllSbrIdleQualifierEnable;
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UINT32 LpmPriVal; ///< Low Power Mode Priority
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} PMC_SOC_CONFIG;
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typedef struct {
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BOOLEAN OverrideFetRampTime;
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UINT8 FetRampTime;
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UINT8 IsFetRampTime;
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UINT16 FuseDownloadDelayUs;
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} PMC_FIVR_SOC_CONFIG;
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#endif
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