63 lines
3.2 KiB
Plaintext
63 lines
3.2 KiB
Plaintext
//
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// Automatically generated by GenNvs ver 2.4.6
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// Please DO NOT modify !!!
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//
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/**@file
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2018 - 2019 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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//
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// Define ITBT NVS Area operation region.
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//
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OperationRegion(ITNV,SystemMemory,ITNB,ITNL)
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Field(ITNV,AnyAcc,Lock,Preserve)
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{ Offset(0), ITSP, 8, // Offset(0), Enable/Disable Integrated TbtSupport
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Offset(1), IDM0, 8, // Offset(1), Integrated DMA0 is supported or not.
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Offset(2), IDM1, 8, // Offset(2), Integrated DMA1 is supported or not.
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Offset(3), ITCP, 8, // Offset(3), Current Port that has plug event.
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Offset(4), IT0E, 8, // Offset(4), ITbt Pcie Root Port 0 is enabled or not.
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Offset(5), IT1E, 8, // Offset(5), ITbt Pcie Root Port 1 is enabled or not.
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Offset(6), IT2E, 8, // Offset(6), ITbt Pcie Root Port 2 is enabled or not.
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Offset(7), IT3E, 8, // Offset(7), ITbt Pcie Root Port 3 is enabled or not.
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Offset(8), IORB, 8, // Offset(8), OS Native Resource Balance is enable or not.
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Offset(9), ITRT, 8, // Offset(9), ITBT Rtd3
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Offset(10), ITRE, 16, // Offset(10), ITBT Rtd3 exit delay, unit is ms
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Offset(12), ITIM, 8, // Offset(12), ITBT IMR Valid
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Offset(13), ITFP, 16, // Offset(13), Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for execution of following mailbox communication.
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Offset(15), ITCT, 16, // Offset(15), Timeout value while sending connect topology mailbox command
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Offset(17), ITVD, 8, // Offset(17), ITBT vPro Dock support
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}
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