208 lines
6.9 KiB
C
208 lines
6.9 KiB
C
/** @file
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Header file for USB handle structure definition
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2019 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _USB_HANDLE_H_
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#define _USB_HANDLE_H_
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#include <ConfigBlock.h>
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#include <Usb2PhyConfig.h>
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#include <UsbConfig.h>
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#include <UsbController.h>
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#include <RegisterAccess.h>
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typedef struct _USB_HANDLE USB_HANDLE;
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// USB IP Version enumeration
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typedef enum {
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UNKNOWN,
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V18_0,
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V18_1,
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V19_0,
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V19_1
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} USB_IP_VERSION;
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// USB controller location
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typedef enum {
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Tcss, // Type-C SubSystem
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Standalone // Standalone
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} USB_INTEGRATION;
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// Location stepping
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typedef enum {
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A0,
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A1,
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B0,
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B1,
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C0,
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C1,
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D0,
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D1
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} INTEGRATION_STEPPING;
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// CPX_DEEMPH register structure definition
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typedef union {
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struct {
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UINT32 CminusOnePrecursor : 6; // Bits 0-5
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UINT32 Czero : 6; // Bits 6-11
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UINT32 CplusOnePrecursor : 6; // Bits 12-17
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UINT32 ReservedBits : 14; // Reserved bits
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} Field;
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UINT32 Value;
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} XHCI_CPX_DEEMPH;
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//
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// USB2 PHY reference frequencies values (MHz)
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//
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typedef enum {
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USB_FREQ_19_2 = 0u,
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USB_FREQ_24_0,
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USB_FREQ_96_0,
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USB_FREQ_MAX
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} USB2_PHY_REF_FREQ;
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/**
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Internal USB controller description
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**/
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typedef struct {
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BOOLEAN IsPortResetMessagingSupported; // Holds true if controller supports port reset messaging
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BOOLEAN IsDebugEnabled; // CPU Debug information
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BOOLEAN IsSimulationEnvironment; // Holds information whether code is executed in Simics simulation
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BOOLEAN ExternalPowerControl; // Allow outside agent to configure power and clock gating
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BOOLEAN IsDbcDebugEnabled; // Holds information whether DbC debug is enabled
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/**
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LTV Limit value that will be written to xHCI MMIO 0x8178[12:0] unless it's 0 then it'll be ignored.
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This setting for some PCH's will depend on CPU pairing.
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**/
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UINT16 LtvLimit;
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/**
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xHC Latency Tolerance Parameters used during initialization process
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**/
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UINT32 LtrHigh;
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UINT32 LtrMid;
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UINT32 LtrLow;
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USB_IP_VERSION IpVersion; // USB IP Version
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USB_INTEGRATION Location; // Location of USB controller
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INTEGRATION_STEPPING Stepping; // Stepping of the owner
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BOOLEAN CpxProgramming; // Flag whether to programm CPX_DEEMPH registers
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//
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// Fields with values that will be programmed to CPX registers if CpxProgramming is enabled
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//
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XHCI_CPX_DEEMPH Cp13Deemph; // Value to be set in CP13_DEEMPH register
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XHCI_CPX_DEEMPH Cp14Deemph; // Value to be set in CP14_DEEMPH register
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XHCI_CPX_DEEMPH Cp15Deemph; // Value to be set in CP15_DEEMPH register
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XHCI_CPX_DEEMPH Cp16Deemph; // Value to be set in CP16_DEEMPH register
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BOOLEAN RxStandbySupport; // RxStandby capability flag
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BOOLEAN LaneDeassertInPs3Support; // Lane Deassert in PS3 capability flag
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/**
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This is internal switch which allow skip updating Chipset Init table from IP block flow
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EBG is not supporting updating SUS tables.
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**/
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BOOLEAN SkipWriteToChipsetInitTable;
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/**
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This is an internal switch to allow for enabling/disabling programming around
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xHCI USB2 Debug Mode Back to Back WR support
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**/
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BOOLEAN DisableBackToBackWRSupport;
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USB2_PHY_REF_FREQ Usb2PhyRefFreq; // USB2 PHY Reference Clock frequency
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BOOLEAN EnableHcResetIsolationFlow; // Enables Reset isolation flow triggered for HCRST
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} USB_PRIVATE_CONFIG;
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/**
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Configures HHPIO pins for USB OverCurrent detection
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@param[in] UsbHandle Pointer to USB_HANDLE instance
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@param[in] OvercurrentPin Index of OverCurrent Pin to be enabled
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**/
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typedef
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VOID
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(*USB_ENABLE_OVERCURRENT_PIN) (
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IN USB_HANDLE *UsbHandle,
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IN UINT8 OverCurrentPin
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);
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/**
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Disables USB Controller
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@param[in] UsbHandle Pointer to USB_HANDLE instance
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**/
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typedef
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VOID
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(*USB_CONTROLLER_DISABLE) (
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IN USB_HANDLE *UsbHandle
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);
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/**
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Checks in FIA is given lane is USB owned
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@param[in] UsbHandle Pointer to USB_HANDLE instance
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@param[in] LaneIndex Index of lane to check
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**/
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typedef
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BOOLEAN
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(*USB_LANE_OWNED) (
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IN USB_HANDLE *UsbHandle,
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IN UINT8 LaneNumber
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);
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/**
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USB callbacks
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List of function pointer that can be passed to init library dcfor cross IP calls
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**/
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typedef struct {
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USB_ENABLE_OVERCURRENT_PIN UsbEnableOvercurrentPin;
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USB_CONTROLLER_DISABLE UsbHostControllerDisable;
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USB_CONTROLLER_DISABLE UsbDeviceControllerDisable;
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USB_LANE_OWNED UsbIsLaneOwned;
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} USB_CALLBACK;
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/**
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USB controller handle. Stores all data needed for USB IP initialization
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**/
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struct _USB_HANDLE {
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USB_CONTROLLER *HostController;
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USB_CONTROLLER *DeviceController;
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USB_CONFIG *UsbConfig;
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USB2_PHY_CONFIG *Usb2PhyConfig;
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USB_PRIVATE_CONFIG *PrivateConfig;
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USB_CALLBACK *Callback;
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REGISTER_ACCESS *Usb2SbAccessPrivateControl; /* P2SB Message type, USB2 controller Private Config Register (PCR) space access */
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REGISTER_ACCESS *DciSbAccessMmio; /* P2SB MMIO type, DCI controller Private Config Register (PCR) space access */
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REGISTER_ACCESS *XhciSbAccessMmio; /* P2SB MMIO type, XHCI controller Private Config Register (PCR) space access */
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UINT64 Mmio; /* USB Temporary Bar */
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};
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#endif// _USB_HANDLE_H_
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