57 lines
1.6 KiB
NASM
57 lines
1.6 KiB
NASM
;; @file
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; Assembly code of Cpu
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;
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;@copyright
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; INTEL CONFIDENTIAL
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; Copyright (c) 2017 - 2018 Intel Corporation. All rights reserved.
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;;
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IA32_CR4_OSFXSR equ 200h
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IA32_CR4_OSXMMEXCPT equ 400h
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IA32_CR0_MP equ 2h
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IA32_CPUID_SSE2 equ 02000000h
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IA32_CPUID_SSE2_B equ 26
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SECTION .text
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;------------------------------------------------------------------------------
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; Set up flags in CR4 for XMM instruction enabling
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;------------------------------------------------------------------------------
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global ASM_PFX(InitXmm)
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ASM_PFX(InitXmm):
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push ebx
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; Check whether SSE2 is supported
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mov eax, 1
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cpuid
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bt edx, IA32_CPUID_SSE2_B
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jnc .skipxmm
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; Enable XMM
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mov eax, cr0
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or eax, IA32_CR0_MP
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mov cr0, eax
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mov eax, cr4
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or eax, IA32_CR4_OSFXSR
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or eax, IA32_CR4_OSXMMEXCPT
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mov cr4, eax
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.skipxmm:
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pop ebx
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ret
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;------------------------------------------------------------------------------
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; Invalidate cache
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;------------------------------------------------------------------------------
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global ASM_PFX(CacheInvd)
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ASM_PFX(CacheInvd):
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invd
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ret
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