57 lines
2.0 KiB
Plaintext
57 lines
2.0 KiB
Plaintext
/**@file
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@copyright
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INTEL CONFIDENTIAL
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Copyright (c) 2015 - 2017 Intel Corporation. All rights reserved
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This software and associated documentation (if any) is furnished
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under a license and may only be used or copied in accordance
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with the terms of the license. Except as permitted by the
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license, no part of this software or documentation may be
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reproduced, stored in a retrieval system, or transmitted in any
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form or by any means without the express written consent of
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Intel Corporation.
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This file contains an 'Intel Peripheral Driver' and is uniquely
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identified as "Intel Reference Module" and is licensed for Intel
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CPUs and chipsets under the terms of your license agreement with
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Intel or your vendor. This file may be modified by the user, subject
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to additional terms of the license agreement.
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@par Specification Reference:
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**/
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//
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// Definition for MSPDRTREQ bits, which are used for ASL code to
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// trigger requests for ModPHY SPD gating.
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//
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#ifndef _HSIO_DEFINE_ASL_
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#define _HSIO_DEFINE_ASL_
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#define MODPHY_SPD_GATING_PCIE_RP1 0
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#define MODPHY_SPD_GATING_PCIE_RP2 1
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#define MODPHY_SPD_GATING_PCIE_RP3 2
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#define MODPHY_SPD_GATING_PCIE_RP4 3
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#define MODPHY_SPD_GATING_PCIE_RP5 4
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#define MODPHY_SPD_GATING_PCIE_RP6 5
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#define MODPHY_SPD_GATING_PCIE_RP7 6
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#define MODPHY_SPD_GATING_PCIE_RP8 7
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#define MODPHY_SPD_GATING_PCIE_RP9 8
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#define MODPHY_SPD_GATING_PCIE_RP10 9
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#define MODPHY_SPD_GATING_PCIE_RP11 10
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#define MODPHY_SPD_GATING_PCIE_RP12 11
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#define MODPHY_SPD_GATING_PCIE_RP13 12
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#define MODPHY_SPD_GATING_PCIE_RP14 13
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#define MODPHY_SPD_GATING_PCIE_RP15 14
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#define MODPHY_SPD_GATING_PCIE_RP16 15
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#define MODPHY_SPD_GATING_PCIE_RP17 16
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#define MODPHY_SPD_GATING_PCIE_RP18 17
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#define MODPHY_SPD_GATING_PCIE_RP19 18
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#define MODPHY_SPD_GATING_PCIE_RP20 19
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#define MODPHY_SPD_GATING_SATA 20
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#define MODPHY_SPD_GATING_GBE 21
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#define MODPHY_SPD_GATING_XHCI 22
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#define MODPHY_SPD_GATING_XDCI 23
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#define MODPHY_SPD_GATING_UFS 24
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#endif // _HSIO_DEFINE_ASL_
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