138 lines
3.9 KiB
C
138 lines
3.9 KiB
C
/** @file
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PCH SMM private lib.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2018 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include <Uefi/UefiBaseType.h>
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#include <Library/BaseLib.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/CpuPlatformLib.h>
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#include <CpuRegs.h>
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#include <Register/CommonMsr.h>
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#include <Register/PttPtpRegs.h>
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STATIC UINT32 mBiosGuardEnabled = ~0u;
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/**
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Set InSmm.Sts bit
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**/
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VOID
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PchSetInSmmSts (
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VOID
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)
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{
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UINT32 Data32;
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//
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// When BIOS GUARD is enabled, the MSR 1FEh is invalid.
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//
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if (mBiosGuardEnabled != 0) {
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if (mBiosGuardEnabled == 1) {
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return;
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}
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mBiosGuardEnabled = IsBiosGuardEnabled () ? 1 : 0;
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if (mBiosGuardEnabled == 1) {
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return;
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}
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}
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///
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/// If platform disables TXT_PTLEN strap, NL socket(s) will target abort
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/// when trying to access LT register space below, and writes to
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/// NL's MSR 0x1FE will GP fault. Check straps enabled first.
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///
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Data32 = MmioRead32 (R_LT_EXISTS);
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if (Data32 == 0xFFFFFFFF) {
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return;
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}
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///
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/// Read memory location FED30880h OR with 00000001h, place the result in EAX,
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/// and write data to lower 32 bits of MSR 1FEh (sample code available)
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///
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Data32 = MmioRead32 (R_LT_UCS);
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AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE, Data32 | BIT0);
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///
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/// Read FED30880h back to ensure the setting went through.
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///
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Data32 = MmioRead32 (R_LT_UCS);
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}
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/**
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Clear InSmm.Sts bit
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**/
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VOID
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PchClearInSmmSts (
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VOID
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)
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{
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UINT32 Data32;
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//
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// When BIOS GUARD is enabled, the MSR 1FEh is invalid.
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//
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if (mBiosGuardEnabled != 0) {
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if (mBiosGuardEnabled == 1) {
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return;
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}
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mBiosGuardEnabled = IsBiosGuardEnabled () ? 1 : 0;
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if (mBiosGuardEnabled == 1) {
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return;
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}
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}
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///
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/// If platform disables TXT_PTLEN strap, NL socket(s) will target abort
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/// when trying to access LT register space below, and writes to
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/// NL's MSR 0x1FE will GP fault. Check straps enabled first.
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///
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Data32 = MmioRead32 (R_LT_EXISTS);
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if (Data32 == 0xFFFFFFFF) {
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return;
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}
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///
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/// Read memory location FED30880h AND with FFFFFFFEh, place the result in EAX,
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/// and write data to lower 32 bits of MSR 1FEh (sample code available)
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///
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Data32 = MmioRead32 (R_LT_UCS);
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AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE, Data32 & (UINT32) (~BIT0));
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///
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/// Read FED30880h back to ensure the setting went through.
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///
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Data32 = MmioRead32 (R_LT_UCS);
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}
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