375 lines
9.7 KiB
Plaintext
375 lines
9.7 KiB
Plaintext
/** @file
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This file contains the CPU PCIe Root Port configuration
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2018 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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External(LTRX) // CPU PCIe Root Port 0 Latency Tolerance Reporting Enable
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External(LTRY) // CPU PCIe Root Port 1 Latency Tolerance Reporting Enable
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External(LTRZ) // CPU PCIe Root Port 2 Latency Tolerance Reporting Enable
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External(LTRW) // CPU PCIe Root Port 3 Latency Tolerance Reporting Enable
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External(SMSL) // CPU PCIe Root Port Latency Tolerance Reporting Max Snoop Latency
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External(SNSL) // CPU PCIe Root Port Latency Tolerance Reporting Max No Snoop Latency
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External(PG0E) // CpuPcieRp0Enable <b>0: Disable</b>; 1: Enable
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External(PG1E) // CpuPcieRp1Enable <b>0: Disable</b>; 1: Enable
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External(PG2E) // CpuPcieRp2Enable <b>0: Disable</b>; 1: Enable
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External(PG3E) // CpuPcieRp3Enable <b>0: Disable</b>; 1: Enable
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External(\_SB.PC00.PEG0, DeviceObj)
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External(\_SB.PC00.PEG0._ADR, MethodObj)
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External(\_SB.PC00.PEG1, DeviceObj)
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External(\_SB.PC00.PEG1._ADR, MethodObj)
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External(\_SB.PC00.PEG2, DeviceObj)
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External(\_SB.PC00.PEG2._ADR, MethodObj)
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External(\_SB.PC00.PEG3, DeviceObj)
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External(\_SB.PC00.PEG3._ADR, MethodObj)
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External(\_SB.PC00.PEG0.PEGP, DeviceObj)
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External(\_SB.PC00.PEG1.PEGP, DeviceObj)
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External(\_SB.PC00.PEG2.PEGP, DeviceObj)
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External(\_SB.PC00.PEG3.PEGP, DeviceObj)
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External(\AR02)
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External(\PD02)
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External(\AR0A)
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External(\PD0A)
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External(\AR0B)
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External(\PD0B)
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External(\AR0C)
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External(\PD0C)
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External(VMDE)
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External(VMCP)
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External(MPGN)
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External(PINI, MethodObj) // Platform specific PCIe root port initialization.
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External(PBR1)
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External(PBR2)
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External(PBR3)
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External(\STD3, FieldUnitObj) // 0: D3 disable. 1: D3Hot support for Storages. 2: D3Cold support for Storages.
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External(\PPA0, IntObj)
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External(\PPA1, IntObj)
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External(\PPA2, IntObj)
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External(\PPA3, IntObj)
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External(CPID)
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Scope (\_SB.PC00.PEG0) {
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Name(SLOT, 0) // CPU PCIe root port index 0 corresponds to PEG60 (0/6/0)
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Method (CPRA, 0x0, NotSerialized) {
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If(LNotEqual(\PPA0,0)) {
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Return (\PPA0)
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} Else {
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Return (0x00060000)
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}
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}
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Method (_STA, 0x0, NotSerialized) {
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if(PG0E == 1) { // If CPU PCIe RP0 enabled?
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Return(0x0F)
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}
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Return(0x00)
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}
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Name(LTEN, 0)
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Name(LMSL, 0)
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Name(LNSL, 0)
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Method(_INI)
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{
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If(PRES()) {
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Store (LTRX, LTEN)
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Store (SMSL, LMSL)
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Store (SNSL, LNSL)
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If(CondRefOf(PINI)) {PINI()}
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If(LAnd(CondRefOf(VMCP),CondRefOf(VMDE))) {
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If(LAnd(LEqual(VMDE,1),LNotEqual(And(VMCP,0x8),0))) {
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Store (1, PRMV)
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}
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}
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//
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// RP D3Cold/D3hot support status for Storage devices
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//
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#define CPU_PCIE_ROOT_PORT \_SB.PC00.PEG0
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Include ("CpuPcieStorage.asl")
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#undef CPU_PCIE_ROOT_PORT
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}
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}
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Method(_PRT,0) {
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If(PICM) {
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Return(AR02)
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} // APIC mode
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Return (PD02) // PIC Mode
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} // end _PRT
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Include("CpuPcieRpCommon.asl")
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} // PEG0 scope end
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Scope (\_SB.PC00.PEG1) {
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Name(SLOT, 1) // CPU PCIe root port index 1 corresponds to PEG10 (0/1/0)
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Method (CPRA, 0x0, NotSerialized) {
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If(LNotEqual(\PPA1,0)) {
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Return (\PPA1)
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} Else {
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Return (0x00010000)
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}
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}
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Method (_STA, 0x0, NotSerialized) {
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if(PG1E == 1) { // If CPU PCIe RP1 enabled?
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Return(0x0F)
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}
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Return(0x00)
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}
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Name(LTEN, 0)
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Name(LMSL, 0)
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Name(LNSL, 0)
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Method(_INI)
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{
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If(PRES()) {
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Store (LTRY, LTEN)
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Store (SMSL, LMSL)
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Store (SNSL, LNSL)
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If(CondRefOf(PINI)) {PINI()}
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If(LAnd(CondRefOf(VMCP),CondRefOf(VMDE))) {
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If(LAnd(LEqual(VMDE,1),LNotEqual(And(VMCP,0x1),0))) {
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Store (1, PRMV)
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}
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}
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//
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// RP D3Cold/D3hot support status for Storage devices
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//
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#define CPU_PCIE_ROOT_PORT \_SB.PC00.PEG1
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Include ("CpuPcieStorage.asl")
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#undef CPU_PCIE_ROOT_PORT
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}
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}
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Method(_PRT,0) {
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If(PICM) {
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Return(AR02)
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} // APIC mode
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Return (PD02) // PIC Mode
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} // end _PRT
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Include("CpuPcieRpCommon.asl")
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} // PEG1 scope end
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Scope (\_SB.PC00.PEG2) {
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Name(SLOT, 2)
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Method (CPRA, 0x0, NotSerialized) {
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If (LNotEqual(\PPA2,0)) {
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Return (\PPA2)
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} Else {
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Return (0x00010001)
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}
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}
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Method (_STA, 0x0, NotSerialized) {
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if(PG2E == 1) { // If CPU PCIe RP2 enabled?
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Return(0x0F)
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}
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Return(0x00)
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}
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Name(LTEN, 0)
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Name(LMSL, 0)
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Name(LNSL, 0)
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Method(_INI)
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{
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If(PRES()) {
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Store (LTRZ, LTEN)
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Store (SMSL, LMSL)
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Store (SNSL, LNSL)
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If(CondRefOf(PINI)) {PINI()}
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If(LAnd(CondRefOf(VMCP),CondRefOf(VMDE))) {
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If(LAnd(LEqual(VMDE,1),LOr(LNotEqual(And(VMCP,0x2),0), LNotEqual(And(VMCP,0x10),0)))) {
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Store (1, PRMV)
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}
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}
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//
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// RP D3Cold/D3hot support status for Storage devices
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//
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#define CPU_PCIE_ROOT_PORT \_SB.PC00.PEG2
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Include ("CpuPcieStorage.asl")
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#undef CPU_PCIE_ROOT_PORT
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}
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}
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Method(_PRT,0) {
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If (LEqual (And (CPID, 0xFFFFFFF0), 0x000906A0)) {
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//
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// For SIP based PCIe controllers, INTx swizzle should be based on per controller ports.
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// IRQ mapping should be same for the first root port of all controllers as per HW design.
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// Remaining root ports can have different mapping
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//
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If (PICM) {
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Return (AR02)
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} // APIC mode
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Return (PD02) // PIC Mode
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} Else {
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If(PICM) {
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Return(AR0A)
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} // APIC mode
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Return (PD0A) // PIC Mode
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}
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} // end _PRT
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Include("CpuPcieRpCommon.asl")
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} // PEG2 scope end
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If (CondRefOf(\_SB.PC00.PEG3)) {
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Scope (\_SB.PC00.PEG3) {
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Name(SLOT, 3) // CPU PCIe root port index 3 corresponds to PEG12 (0/1/2)
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Method (CPRA, 0x0, NotSerialized) {
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If(LNotEqual(\PPA3,0)) {
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Return (\PPA3)
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} Else {
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Return (0x00010002)
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}
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}
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Method (_STA, 0x0, NotSerialized) {
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if(PG3E == 1) { // If CPU PCIe RP3 enabled?
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Return(0x0F)
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}
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Return(0x00)
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}
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Name(LTEN, 0)
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Name(LMSL, 0)
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Name(LNSL, 0)
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Method(_INI)
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{
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If(PRES()) {
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Store (LTRW, LTEN)
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Store (SMSL, LMSL)
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Store (SNSL, LNSL)
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If(CondRefOf(PINI)) {PINI()}
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If(LAnd(CondRefOf(VMCP),CondRefOf(VMDE))) {
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If(LAnd(LEqual(VMDE,1),LNotEqual(And(VMCP,0x4),0))) {
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Store (1, PRMV)
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}
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}
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//
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// RP D3Cold/D3hot support status for Storage devices
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//
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#define CPU_PCIE_ROOT_PORT \_SB.PC00.PEG3
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Include ("CpuPcieStorage.asl")
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#undef CPU_PCIE_ROOT_PORT
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}
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}
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Method(_PRT,0) {
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If(PICM) {
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Return(AR0B)
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} // APIC mode
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Return (PD0B) // PIC Mode
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} // end _PRT
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Include("CpuPcieRpCommon.asl")
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} // PEG3 scope end
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}
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Scope(\_SB.PC00.PEG0.PEGP) {
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include ("PcieEpSel.asl")
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Method(_PRW, 0) {
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Return(GPRW(0x69, 4)) // can wakeup from S4 state
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}
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}
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If (PBR1) {
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Scope(\_SB.PC00.PEG1.PEGP) {
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Method(_S0W, 0) { Return(4)} //D3cold is supported
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Device (PEGD) {
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Method(_S0W, 0) { Return(4)} //D3cold is supported
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Name(_ADR, 0x00000000)
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Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state
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}
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} // end "P.E.G. Port Slot x16"
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}
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Scope(\_SB.PC00.PEG1.PEGP) {
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include ("PcieEpSel.asl")
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Method(_PRW, 0) {
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Return(GPRW(0x69, 4)) // can wakeup from S4 state
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}
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}
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If (PBR2) {
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Scope(\_SB.PC00.PEG2.PEGP) {
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Method(_S0W, 0) { Return(4)} //D3cold is supported
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Device (PEGD) {
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Method(_S0W, 0) { Return(4)} //D3cold is supported
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Name(_ADR, 0x00000000)
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Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state
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}
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} // end "P.E.G. Port Slot 2x8"
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}
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Scope(\_SB.PC00.PEG2.PEGP) {
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include ("PcieEpSel.asl")
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Method(_PRW, 0) {
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Return(GPRW(0x69, 4)) // can wakeup from S4 state
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}
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}
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If (PBR3) {
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Scope(\_SB.PC00.PEG3.PEGP) {
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Method(_S0W, 0) { Return(4)} //D3cold is supported
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Device (PEGD) {
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Method(_S0W, 0) { Return(4)} //D3cold is supported
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Name(_ADR, 0x00000000)
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Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 state
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}
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} // end "P.E.G. Port Slot 1x8 - 2x4"
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}
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If (CondRefOf(\_SB.PC00.PEG3)) {
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Scope(\_SB.PC00.PEG3.PEGP) {
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include ("PcieEpSel.asl")
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Method(_PRW, 0) {
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Return(GPRW(0x69, 4)) // can wakeup from S4 state
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}
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}
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}
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