409 lines
13 KiB
Plaintext
409 lines
13 KiB
Plaintext
/** @file
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;******************************************************************************
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;* Copyright 2021 Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corp.
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;*
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;******************************************************************************
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*/
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/** @file
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This file contains the PCIe Root Port Common configuration
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2018 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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External(ECR1)
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External(GPRW, MethodObj)
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External(PICM)
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External(\_SB.PC00.PC2M, MethodObj)
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External(PPBA, MethodObj) // PCIe power budget allocation
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External(UPRD, MethodObj) // PCIe update PERST# assertion delay
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External(PPS0, MethodObj) // Platform specific PCIe root port _PS0 Hook Function.
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External(PPS3, MethodObj) // Platform specific PCIe root port _PS3 Hook Function.
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Name (PRTP, PCIE_RP_TYPE_CPU) // PCIE RP TYPE
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OperationRegion(PXCS,SystemMemory,\_SB.PC00.PC2M(_ADR ()),0x480)
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Field(PXCS,AnyAcc, NoLock, Preserve)
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{
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Offset(0),
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VDID, 32,
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Offset(0x50), // LCTL - Link Control Register
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L0SE, 1, // 0, L0s Entry Enabled
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, 3,
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LDIS, 1,
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, 3,
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Offset(0x52), // LSTS - Link Status Register
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, 13,
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LASX, 1, // 0, Link Active Status
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Offset(0x5A), // SLSTS[7:0] - Slot Status Register
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ABPX, 1, // 0, Attention Button Pressed
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, 2,
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PDCX, 1, // 3, Presence Detect Changed
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, 2,
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PDSX, 1, // 6, Presence Detect State
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, 1,
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Offset(0x60), // RSTS - Root Status Register
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, 16,
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PSPX, 1, // 16, PME Status
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Offset(0xA4), // PMCSR
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D3HT, 2, // PowerState
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Offset(0xD8), // 0xD8, MPC - Miscellaneous Port Configuration Register
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, 30,
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HPEX, 1, // 30, Hot Plug SCI Enable
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PMEX, 1, // 31, Power Management SCI Enable
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Offset(0xE0), // 0xE0, SPR - Scratch Pad Register
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//[-start-210816-IB05660174-add]//
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, 0,
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//[-end-210816-IB05660174-add]//
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SCB0, 1, // Scratchpad register SPR[0] (SCB)
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, 6,
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NCB7, 1, // Non-Sticky Scratch Pad Bit (NSCB)[7]
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Offset(0xE2), // 0xE2, RPPGEN - Root Port Power Gating Enable
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, 2,
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L23E, 1, // 2, L23_Rdy Entry Request (L23ER)
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L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
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Offset(0x324), // 0x324 - PCIEDBG
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, 3,
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LEDM, 1, // PCIEDBG.DMIL1EDM
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Offset(0x328), // 0x328, PCI Express Status 1
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, 24,
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LTSM, 8,
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}
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Field(PXCS,AnyAcc, NoLock, WriteAsZeros)
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{
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Offset(0xDC), // 0xDC, SMSCS - SMI/SCI Status Register
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, 30,
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HPSX, 1, // 30, Hot Plug SCI Status
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PMSX, 1 // 31, Power Management SCI Status
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}
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//
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// L23D method recovers link from L2 or L3 state. Used for RTD3 flows, right after endpoint is powered up and exits reset.
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// This flow is implemented in ASL because rootport registers used for L2/L3 entry/exit
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// are proprietary and OS drivers don't know about them.
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//
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Method (L23D, 0, Serialized) {
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If(LNotEqual(SCB0,0x1)) {
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Return()
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}
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/// Set L23_Rdy to Detect Transition (L23R2DT)
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Store(1, L23R)
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Store(0, Local0)
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/// Wait for transition to Detect
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While(L23R) {
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If(Lgreater(Local0, 4))
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{
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Break
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}
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Sleep(16)
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Increment(Local0)
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}
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Store(0,SCB0)
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/// Once in Detect, wait up to 124 ms for Link Active (typically happens in under 70ms)
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/// Worst case per PCIe spec from Detect to Link Active is:
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/// 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config (24+2+2+2+2)
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Store(0, Local0)
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While(LEqual(LASX,0)) {
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If(Lgreater(Local0, 8))
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{
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Break
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}
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Sleep(16)
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Increment(Local0)
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}
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}
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//
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// DL23 method puts link to L2 or L3 state. Used for RTD3 flows, before endpoint is powered down.
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// This flow is implemented in ASL because rootport registers used for L2/L3 entry/exit
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// are proprietary and OS drivers don't know about them.
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//
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Method (DL23, 0, Serialized) {
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Store(1, L23E)
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Sleep(16)
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Store(0, Local0)
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While(L23E) {
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If(Lgreater(Local0, 4))
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{
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Break
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}
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Sleep(16)
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Increment(Local0)
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}
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Store(1,SCB0)
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}
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Name(LTRV, Package(){0,0,0,0})
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Name(PRMV, 0) // PCIE Rp Mapped under VMD
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Name(RD3C, 2) // 2: D3Cold support for Storage connected to PCIE port, 1: D3Hot support for Storage connected to PCIE port,
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// 0: D3 unsupport for Storage connected to PCIE port. By default this is set as 1 for other EndPoints
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//
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// Check if root port is present.
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// @return 0: root port is disabled, 1: root port is enabled
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//
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Method(PRES) {
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If (LEqual (VDID, 0xFFFFFFFF)) {
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Return(0)
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} Else {
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Return(1)
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}
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}
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//
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// _DSM Device Specific Method
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//
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// Arg0: UUID Unique function identifier
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// Arg1: Integer Revision Level
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// Arg2: Integer Function Index (0 = Return Supported Functions)
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// Arg3: Package Parameters
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Method(_DSM, 4, Serialized) {
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//
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// Switch based on which unique function identifier was passed in
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//
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If (LEqual(Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
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//
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// _DSM Definitions for Latency Tolerance Reporting
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//
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// Arguments:
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// Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
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// Arg1: Revision ID: 3
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// Arg2: Function Index: 0, 6, 8, 9
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// Arg3: Empty Package
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//
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// Switch by function index
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//
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Switch(ToInteger(Arg2)) {
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//
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// Function Index:0
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// Standard query - A bitmask of functions supported
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//
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Case (0) {
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Name(OPTS,Buffer(2){0,0})
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CreateBitField(OPTS,0,FUN0)
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CreateBitField(OPTS,6,FUN6)
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CreateBitField(OPTS,8,FUN8)
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CreateBitField(OPTS,9,FUN9)
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CreateBitField(OPTS,10,FUNA)
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CreateBitField(OPTS,11,FUNB)
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if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
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Store(1,FUN0)
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if (LNotEqual (LTEN, 0)) {
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Store(1,FUN6)
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}
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If(CondRefOf(ECR1)) {
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if(LEqual(ECR1,1)){
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if (LGreaterEqual(Arg1, 3)){ // test Arg1 for Revision ID: 3
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Store(1,FUN8)
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Store(1,FUN9)
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}
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}
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}
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}
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If (LGreaterEqual(Arg1, 4)) { //test Arg1 for Revision ID: 4
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If(CondRefOf(PPBA)) {
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Store(1,FUNA)
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}
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If(CondRefOf(UPRD)) {
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Store(1,FUNB)
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}
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}
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Return (OPTS)
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}
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//
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// Function Index: 6
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// LTR Extended Capability Structure
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//
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Case(6) {
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if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
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Store(And(ShiftRight(LMSL,10),7), Index(LTRV, 0))
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Store(And(LMSL,0x3FF), Index(LTRV, 1))
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Store(And(ShiftRight(LNSL,10),7), Index(LTRV, 2))
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Store(And(LNSL,0x3FF), Index(LTRV, 3))
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Return (LTRV)
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}
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}
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Case(8) { //ECR ACPI additions for FW latency optimizations, DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume
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If(CondRefOf(ECR1)) {
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if(LEqual(ECR1,1)){
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if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3
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return (1)
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}
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}
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}
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}
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Case(9) { //ECR ACPI additions for FW latency optimizations, DSM for Specifying Device Readiness Durations
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If(CondRefOf(ECR1)) {
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if(LEqual(ECR1,1)){
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if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3
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return(Package(5){50000,Ones,Ones,50000,Ones})
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}
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}
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}
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}
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//
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// Function index 10 - negotiate device auxilary power consumption.
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//
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Case(10) {
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If(CondRefOf(PPBA)) {
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Return(PPBA(Arg3))
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}
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}
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//
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// Function index 11 update delay between PME_TO_Ack and PERST# assertion
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//
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Case(11) {
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If(CondRefOf(UPRD)) {
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Return(UPRD(Arg3))
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}
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}
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} // End of switch(Arg2)
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} // End of if
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return (Buffer() {0x00})
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} // End of _DSM
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Method(_PRW, 0) {
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Return(GPRW(0x69, 4)) // can wakeup from S4 state
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}
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Method (_PS0, 0, Serialized)
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{
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If (LEqual (HPEX, 1)) {
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Store (0, HPEX) // Disable Hot Plug SCI
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Store (1, HPSX) // Clear Hot Plug SCI status
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}
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If (LEqual (PMEX, 1)) {
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Store (0, PMEX) // Disable Power Management SCI
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Store (1, PMSX) // Clear Power Management SCI status
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}
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If (CondRefOf (PPS0)) {
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PPS0 ()
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}
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}
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Method (_PS3, 0, Serialized)
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{
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If (CondRefOf (PPS3)) {
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PPS3 ()
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}
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If (LEqual (HPEX, 0)) {
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Store(1, HPEX) // Enable Hot Plug SCI
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Store(1, HPSX) // Clear Hot Plug SCI status
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}
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If (LEqual(PMEX, 0)) {
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Store(1, PMEX) // Enable Power Management SCI
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Store(1, PMSX) // Clear Power Management SCI status
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}
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}
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Method (_DSD, 0) {
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If(CondRefOf(PINI)) {
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Return (
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Package () {
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ToUUID ("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"),
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Package () {
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Package (2) {"HotPlugSupportInD3", 1},
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},
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ToUUID("FDF06FAD-F744-4451-BB64-ECD792215B10"),
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Package () {
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Package (2) {"FundamentalDeviceResetTriggeredOnD3ToD0", 1},
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},
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// This _DSD object informs Windows PCIe bus driver that
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// this root ports supports auxilary power budgeting.
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ToUUID("6B4AD420-8FD3-4364-ACF8-EB94876FD9EB"),
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Package () {
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}
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}
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) //End of Return ()
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} else {
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Return (
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Package () {
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ToUUID ("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"),
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Package () {
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Package (2) {"HotPlugSupportInD3", 1},
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},
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ToUUID("FDF06FAD-F744-4451-BB64-ECD792215B10"),
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Package () {
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Package (2) {"FundamentalDeviceResetTriggeredOnD3ToD0", 1},
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}
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}
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) // End of Return ()
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}
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}
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//
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// PCI_EXP_STS Handler for PCIE Root Port
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//
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Method(HPME,0,Serialized) {
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If(LAnd(LNotEqual(VDID,0xFFFFFFFF), LEqual(PMSX,1))) { //if port exists and has PME SCI Status set...
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Store(1,PMSX) // clear rootport's PME SCI status
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Store(1,PSPX) // consume one pending PME status to prevent it from blocking the queue
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Return(0x01)
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}
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Return(0x00)
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}
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//
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// Sub-Method of _L61 Hot-Plug event
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// _L61 event handler should invoke this method to support HotPlug wake event from PEG RP
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//
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Method(HPEV,0,Serialized) {
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If(LAnd(LNotEqual(VDID,0xFFFFFFFF), HPSX)) {
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// Clear HotPlug SCI event status
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Store(1, HPSX)
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If(LEqual(PDCX, 1)) {
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// Clear Presence Detect Changed
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Store(1,PDCX)
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If(LEqual(PDSX, 0)) {
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// The PCI Express slot is empty, so disable L0s on hot unplug
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//
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Store(0,L0SE)
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}
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// Perform proper notification
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// to the OS.
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Notify(^,0)
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}
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}
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}
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