106 lines
3.8 KiB
Plaintext
106 lines
3.8 KiB
Plaintext
/** @file
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This file contains the device definitions of the SystemAgent
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PCIE ACPI Reference Code.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2019 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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External(\_SB.ISME, MethodObj)
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External(\_SB.SHPO, MethodObj)
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External(\_SB.CAGS, MethodObj)
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External(\_SB.PC00.PEG0, DeviceObj)
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External(\_SB.PC00.PEG1, DeviceObj)
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External(\_SB.PC00.PEG2, DeviceObj)
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External(\_SB.PC00.PEG3, DeviceObj)
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External(\_SB.PC00.PEG1.DHDW, MethodObj)
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External(\P0WK)
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External(\P1WK)
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External(\P2WK)
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External(\P3WK)
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//GPE Event handling - Start
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Scope(\_GPE) {
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//
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// _L6F Method call for PEG0/1/2/3 ports to handle 2-tier RTD3 GPE events
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//
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Method(P0L6,0)
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{
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// PEG0 Device Wake Event
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If (\_SB.ISME(P0WK))
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{
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\_SB.SHPO(P0WK, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
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Notify(\_SB.PC00.PEG0, 0x02) // device wake
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\_SB.CAGS(P0WK) // Clear GPE status bit for PEG0 WAKE
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}
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}
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Method(P1L6,0)
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{
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// PEG1 Device Wake Event
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If (\_SB.ISME(P1WK))
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{
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If (CondRefOf (\_SB.PC00.PEG1.DHDW)) { // DG support HPD as D3 Wake GPIO and DHDW exists
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\_SB.PC00.PEG1.DHDW () // Disable Discrete Graphics HPD SCI implementated As D3 Wake GPIO
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Notify(\_SB.PC00.PEG1, 0x00) // Bus Check
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} Else {
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\_SB.SHPO(P1WK, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
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Notify(\_SB.PC00.PEG1, 0x02) // device wake
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}
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\_SB.CAGS(P1WK) // Clear GPE status bit for PEG1 WAKE
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}
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}
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Method(P2L6,0)
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{
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// PEG2 Device Wake Event
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If (\_SB.ISME(P2WK))
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{
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\_SB.SHPO(P2WK, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
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Notify(\_SB.PC00.PEG2, 0x02) // device wake
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\_SB.CAGS(P2WK) // Clear GPE status bit for PEG2 WAKE
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}
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}
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If (CondRefOf(\_SB.PC00.PEG3)) {
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Method(P3L6,0)
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{
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// PEG2 Device Wake Event
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If (\_SB.ISME(P3WK))
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{
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\_SB.SHPO(P3WK, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
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Notify(\_SB.PC00.PEG3, 0x02) // device wake
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\_SB.CAGS(P3WK) // Clear GPE status bit for PEG2 WAKE
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}
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}
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}
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} //Scope(\_GPE)
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