172 lines
9.0 KiB
C
172 lines
9.0 KiB
C
/** @file
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This protocol provides the memory information data, such as
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total physical memory size, memory frequency, memory size
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of each dimm and rank.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 1999 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _MEM_INFO_PROTOCOL_H_
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#define _MEM_INFO_PROTOCOL_H_
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//
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// Extern the GUID for protocol users.
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//
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extern EFI_GUID gMemInfoProtocolGuid;
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//
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// Protocol definitions
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//
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#define NODE_NUM 2
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#define CH_NUM 4
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#define DIMM_NUM 2
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#define RANK_NUM 2
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#define SLOT_NUM (NODE_NUM * CH_NUM * DIMM_NUM)
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#define PROFILE_NUM 7 // number of memory profiles supported
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//
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// Matches MrcDdrType enum in MRC
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//
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#ifndef MRC_DDR_TYPE_DDR4
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#define MRC_DDR_TYPE_DDR4 0
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#endif
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#ifndef MRC_DDR_TYPE_DDR5
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#define MRC_DDR_TYPE_DDR5 1
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#endif
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#ifndef MRC_DDR_TYPE_LPDDR5
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#define MRC_DDR_TYPE_LPDDR5 2
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#endif
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#ifndef MRC_DDR_TYPE_LPDDR4
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#define MRC_DDR_TYPE_LPDDR4 3
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#endif
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#ifndef MRC_DDR_TYPE_UNKNOWN
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#define MRC_DDR_TYPE_UNKNOWN 4
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#endif
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//
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// Matches MrcChannelSts enum in MRC
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//
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#ifndef CHANNEL_NOT_PRESENT
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#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
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#endif
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#ifndef CHANNEL_DISABLED
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#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
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#endif
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#ifndef CHANNEL_PRESENT
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#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
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#endif
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//
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// Matches MrcDimmSts enum in MRC
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//
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#ifndef DIMM_ENABLED
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#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
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#endif
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#ifndef DIMM_DISABLED
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#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
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#endif
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#ifndef DIMM_PRESENT
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#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
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#endif
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#ifndef DIMM_NOT_PRESENT
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#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
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#endif
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#pragma pack(1)
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///
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/// Memory timing Structure
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///
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typedef struct {
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UINT32 tCK; ///< Offset 0 Memory cycle time, in femtoseconds.
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UINT16 NMode; ///< Offset 4 Number of tCK cycles for the channel DIMM's command rate mode.
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UINT16 tCL; ///< Offset 6 Number of tCK cycles for the channel DIMM's CAS latency.
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UINT16 tCWL; ///< Offset 8 Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
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UINT16 tFAW; ///< Offset 10 Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
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UINT16 tRAS; ///< Offset 12 Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
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UINT16 tRCDtRP; ///< Offset 14 Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
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UINT16 tREFI; ///< Offset 16 Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
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UINT16 tRFC; ///< Offset 18 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRFCpb; ///< Offset 20 Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
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UINT16 tRFC2; ///< Offset 22 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRFC4; ///< Offset 24 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRPab; ///< Offset 26 Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
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UINT16 tRRD; ///< Offset 28 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
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UINT16 tRRD_L; ///< Offset 30 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
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UINT16 tRRD_S; ///< Offset 32 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
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UINT16 tRTP; ///< Offset 34 Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
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UINT16 tWR; ///< Offset 36 Number of tCK cycles for the channel DIMM's minimum write recovery time.
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UINT16 tWTR; ///< Offset 38 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
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UINT16 tWTR_L; ///< Offset 40 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
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UINT16 tWTR_S; ///< Offset 42 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
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UINT16 tCCD_L; ///< Offset 44 Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
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UINT8 Rsvd[2]; ///< Offset 46
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} MEMORY_TIMING;
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// @todo use the MemInfoHob data instead of duplicate structure.
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///
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/// Memory information Data Structure
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///
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typedef struct {
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MEMORY_TIMING Timing[PROFILE_NUM]; ///< Offset 0 Timming information for the DIMM
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UINT32 memSize; ///< Offset 128 Total physical memory size
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UINT16 ddrFreq; ///< Offset 132 DDR Current Frequency
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UINT16 ddrFreqMax; ///< Offset 134 DDR Maximum Frequency
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UINT16 dimmSize[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 136 Size of each DIMM
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UINT16 VddVoltage[PROFILE_NUM]; ///< Offset 144(ICL)/168(TGL) The voltage setting for the DIMM
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UINT8 DimmStatus[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 152(ICL)/176(TGL) The enumeration value from MrcDimmSts
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UINT8 RankInDimm[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 156(ICL)/192(TGL) No. of ranks in a dimm
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UINT8 *DimmsSpdData[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 160(ICL)/208(TGL) SPD data of each DIMM
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UINT8 RefClk; ///< Offset 192(ICL)/336(TGL) Reference Clock
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UINT8 Ratio; ///< Offset 193(ICL)/337(TGL) Clock Multiplier
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BOOLEAN EccSupport; ///< Offset 194(ICL)/338(TGL) ECC supported or not
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UINT8 Profile; ///< Offset 195(ICL)/339(TGL) Currently running memory profile
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UINT8 XmpProfileEnable; ///< Offset 196(ICL)/340(TGL): Capability status. 0 is none supported. Bit 0: XMP 1, Bit 1: XMP 2, Bit 2: XMP 3, Bit 3: User 4, Bit 4: User 5.
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UINT8 DdrType; ///< Offset 197(ICL)/341(TGL): Current DDR type, see DDR_TYPE_xxx defines above
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UINT16 Ratio_UINT16; ///< Offset 198(ICL)/342(TGL) Clock Multiplier UINT16
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UINT16 VddqVoltage[PROFILE_NUM]; ///< Offset 200(ICL)/344(TGL) The voltage setting for the DIMM
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UINT16 VppVoltage[PROFILE_NUM]; ///< Offset 208(ICL)/352(TGL) The voltage setting for the DIMM
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BOOLEAN XmpConfigWarning; ///< Offset 216(ICL)/360(TGL) XMP Dimm Config Warning - 1DPC capable but 2DPC is installed
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UINT8 IsDMBRunning; ///< Offset 217(ICL)/361(TGL) Deprecated
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BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population
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BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
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} MEMORY_INFO_DATA;
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#pragma pack()
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///
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/// Memory information Protocol definition
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///
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typedef struct {
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MEMORY_INFO_DATA MemInfoData; ///< Memory Information Data Structure
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} MEM_INFO_PROTOCOL;
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#endif
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