alder_lake_bios/Intel/AlderLake/ClientOneSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIotrapSmi.h

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2.5 KiB
C

/** @file
This file defines the SA Iotrap SMI Protocol to provide the
I/O address for registered Iotrap SMI.
@copyright
INTEL CONFIDENTIAL
Copyright 2013 - 2019 Intel Corporation.
The source code contained or described herein and all documents related to the
source code ("Material") are owned by Intel Corporation or its suppliers or
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and is protected by worldwide copyright and trade secret laws and treaty
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express and approved by Intel in writing.
Unless otherwise agreed by Intel in writing, you may not remove or alter
this notice or any other notice embedded in Materials by Intel or
Intel's suppliers or licensors in any way.
This file contains an 'Intel Peripheral Driver' and is uniquely identified as
"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
the terms of your license agreement with Intel or your vendor. This file may
be modified by the user, subject to additional terms of the license agreement.
@par Specification Reference:
**/
#ifndef _SA_IOTRAP_SMI_PROTOCOL_H_
#define _SA_IOTRAP_SMI_PROTOCOL_H_
//
// Extern the GUID for protocol users.
//
extern EFI_GUID gSaIotrapSmiProtocolGuid;
#define SA_IOTRAP_SMI_PROTOCOL_REVISION_1 1
//
// SA IO Trap SMI Protocol definition (Private protocol for RC internal use only)
//
typedef struct {
/*
Protocol revision number
Any backwards compatible changes to this protocol will result in an update in the revision number
Major changes will require publication of a new protocol
<b>Revision 1</b>:
- First version
*/
UINT8 Revision;
UINT16 SaIotrapSmiAddress;
} SA_IOTRAP_SMI_PROTOCOL;
///
/// Pcie Trap valid types
///
typedef enum {
CpuPciePmTrap,
CpuPcieTrapTypeMaximum
} CPU_PCIE_TRAP_TYPE;
#endif