402 lines
12 KiB
C
402 lines
12 KiB
C
/** @file
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;******************************************************************************
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;* Copyright (c) 2012 - 2019, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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/**
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PCI command register operations supporting functions implementation for PCI Bus module.
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Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "PciBus.h"
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/**
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Operate the PCI register via PciIo function interface.
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@param PciIoDevice Pointer to instance of PCI_IO_DEVICE.
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@param Command Operator command.
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@param Offset The address within the PCI configuration space for the PCI controller.
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@param Operation Type of Operation.
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@param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER.
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@return Status of PciIo operation.
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**/
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EFI_STATUS
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PciOperateRegister (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 Command,
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IN UINT8 Offset,
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IN UINT8 Operation,
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OUT UINT16 *PtrCommand
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)
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{
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UINT16 OldCommand;
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EFI_STATUS Status;
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EFI_PCI_IO_PROTOCOL *PciIo;
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OldCommand = 0;
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PciIo = &PciIoDevice->PciIo;
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if (Operation != EFI_SET_REGISTER) {
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Status = PciIo->Pci.Read (
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PciIo,
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EfiPciIoWidthUint16,
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Offset,
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1,
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&OldCommand
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);
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if (Operation == EFI_GET_REGISTER) {
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*PtrCommand = OldCommand;
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return Status;
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}
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}
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if (Operation == EFI_ENABLE_REGISTER) {
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OldCommand = (UINT16) (OldCommand | Command);
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} else if (Operation == EFI_DISABLE_REGISTER) {
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OldCommand = (UINT16) (OldCommand & ~(Command));
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} else {
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OldCommand = Command;
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}
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return PciIo->Pci.Write (
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PciIo,
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EfiPciIoWidthUint16,
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Offset,
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1,
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&OldCommand
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);
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}
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/**
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Check the capability supporting by given device.
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@param PciIoDevice Pointer to instance of PCI_IO_DEVICE.
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@retval TRUE Capability supportted.
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@retval FALSE Capability not supportted.
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**/
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BOOLEAN
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PciCapabilitySupport (
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IN PCI_IO_DEVICE *PciIoDevice
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)
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{
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if ((PciIoDevice->Pci.Hdr.Status & EFI_PCI_STATUS_CAPABILITY) != 0) {
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return TRUE;
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}
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return FALSE;
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}
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/**
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Locate capability register block per capability ID.
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@param PciIoDevice A pointer to the PCI_IO_DEVICE.
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@param CapId The capability ID.
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@param Offset A pointer to the offset returned.
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@param NextRegBlock A pointer to the next block returned.
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@retval EFI_SUCCESS Successfully located capability register block.
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@retval EFI_UNSUPPORTED Pci device does not support capability.
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@retval EFI_NOT_FOUND Pci device support but can not find register block.
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**/
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EFI_STATUS
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LocateCapabilityRegBlock (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT8 CapId,
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IN OUT UINT8 *Offset,
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OUT UINT8 *NextRegBlock OPTIONAL
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)
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{
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UINT8 CapabilityPtr;
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UINT16 CapabilityEntry;
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UINT8 CapabilityID;
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UINT32 Temp;
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UINTN Count;
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//
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// To check the capability of this device supports
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//
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if (!PciCapabilitySupport (PciIoDevice)) {
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return EFI_UNSUPPORTED;
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}
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if (*Offset != 0) {
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CapabilityPtr = *Offset;
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} else {
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CapabilityPtr = 0;
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if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
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PciIoDevice->PciIo.Pci.Read (
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&PciIoDevice->PciIo,
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EfiPciIoWidthUint8,
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EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
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1,
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&CapabilityPtr
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);
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} else {
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PciIoDevice->PciIo.Pci.Read (
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&PciIoDevice->PciIo,
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EfiPciIoWidthUint32,
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PCI_CAPBILITY_POINTER_OFFSET,
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1,
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&Temp
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);
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//
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// Do not get byte read directly, because some PCI card will return 0xFF
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// when perform PCI-Express byte read, while return correct 0x00
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// when perform PCI-Express dword read, or PCI dword read.
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//
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CapabilityPtr = (UINT8)Temp;
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}
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}
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Count = 0;
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while (CapabilityPtr > 0x3F && Count++ < ((0x100 - 0x40) / sizeof(UINT32))) {
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//
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// Mask it to DWORD alignment per PCI spec
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//
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CapabilityPtr &= 0xFC;
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PciIoDevice->PciIo.Pci.Read (
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&PciIoDevice->PciIo,
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EfiPciIoWidthUint16,
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CapabilityPtr,
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1,
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&CapabilityEntry
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);
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CapabilityID = (UINT8) CapabilityEntry;
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if (CapabilityID == CapId) {
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*Offset = CapabilityPtr;
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if (NextRegBlock != NULL) {
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*NextRegBlock = (UINT8) (CapabilityEntry >> 8);
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}
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return EFI_SUCCESS;
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}
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//
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// Certain PCI device may incorrectly have capability pointing to itself,
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// break to avoid dead loop.
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//
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if (CapabilityPtr == (UINT8) (CapabilityEntry >> 8)) {
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break;
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}
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CapabilityPtr = (UINT8) (CapabilityEntry >> 8);
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}
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return EFI_NOT_FOUND;
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}
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/**
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Locate PciExpress capability register block per capability ID.
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@param PciIoDevice A pointer to the PCI_IO_DEVICE.
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@param CapId The capability ID.
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@param Offset A pointer to the offset returned.
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@param NextRegBlock A pointer to the next block returned.
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@retval EFI_SUCCESS Successfully located capability register block.
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@retval EFI_UNSUPPORTED Pci device does not support capability.
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@retval EFI_NOT_FOUND Pci device support but can not find register block.
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**/
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EFI_STATUS
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LocatePciExpressCapabilityRegBlock (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 CapId,
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IN OUT UINT32 *Offset,
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OUT UINT32 *NextRegBlock OPTIONAL
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)
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{
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EFI_STATUS Status;
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UINT32 CapabilityPtr;
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UINT32 CapabilityEntry;
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UINT16 CapabilityID;
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UINTN Count;
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//
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// To check the capability of this device supports
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//
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if (!PciIoDevice->IsPciExp) {
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return EFI_UNSUPPORTED;
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}
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if (*Offset != 0) {
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CapabilityPtr = *Offset;
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} else {
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CapabilityPtr = EFI_PCIE_CAPABILITY_BASE_OFFSET;
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}
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Count = 0;
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while (CapabilityPtr != 0 && Count++ < ((0x1000 - 0x100) / sizeof(UINT32))) {
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//
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// Mask it to DWORD alignment per PCI spec
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//
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CapabilityPtr &= 0xFFC;
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Status = PciIoDevice->PciIo.Pci.Read (
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&PciIoDevice->PciIo,
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EfiPciIoWidthUint32,
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CapabilityPtr,
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1,
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&CapabilityEntry
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);
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if (EFI_ERROR (Status)) {
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break;
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}
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if (CapabilityEntry == MAX_UINT32) {
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DEBUG ((
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DEBUG_WARN,
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"%a: [%02x|%02x|%02x] failed to access config space at offset 0x%x\n",
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__FUNCTION__,
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PciIoDevice->BusNumber,
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PciIoDevice->DeviceNumber,
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PciIoDevice->FunctionNumber,
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CapabilityPtr
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));
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break;
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}
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CapabilityID = (UINT16) CapabilityEntry;
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if (CapabilityID == CapId) {
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*Offset = CapabilityPtr;
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if (NextRegBlock != NULL) {
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*NextRegBlock = (CapabilityEntry >> 20) & 0xFFF;
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}
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return EFI_SUCCESS;
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}
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CapabilityPtr = (CapabilityEntry >> 20) & 0xFFF;
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}
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return EFI_NOT_FOUND;
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}
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/**
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Locate Capability register by PCI address.
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Pci devices need to get capability reg, but the PciDeviceIo is not ready.
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Using the PciRootBridgeIo protocol instead of PciDeviceIo protocol.
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@param PciRootBridgeIo - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
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@param Pci - Pointer to device's configuration space buffer.
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@param Bus - Bus number.
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@param Device - Device number.
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@param Func - Function number.
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@param CapId - The capability ID.
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@param Offset - A pointer to the offset.
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As input: the default offset;
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As output: the offset of the found block.
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@param NextRegBlock - An optional pointer to return the value of next block.
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@retval EFI_UNSUPPORTED - The Pci Io device is not supported.
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@retval EFI_NOT_FOUND - The Pci Io device cannot be found.
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@retval EFI_SUCCESS - The Pci Io device is successfully located.
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**/
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EFI_STATUS
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LocateCapabilityRegBlockByAddress (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
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IN PCI_TYPE00 *Pci,
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Func,
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IN UINT8 CapId,
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IN OUT UINT8 *Offset,
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OUT UINT8 *NextRegBlock OPTIONAL
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)
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{
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UINT8 CapabilityPtr;
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UINT16 CapabilityEntry;
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UINT8 CapabilityID;
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UINT32 Register;
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UINT64 Address;
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//
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// To check the capability of this device supports
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//
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if (!(Pci->Hdr.Status & EFI_PCI_STATUS_CAPABILITY)) {
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return EFI_UNSUPPORTED;
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}
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if (*Offset != 0) {
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CapabilityPtr = *Offset;
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} else {
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CapabilityPtr = 0;
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if (IS_CARDBUS_BRIDGE (Pci)) {
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Address = EFI_PCI_ADDRESS (Bus, Device, Func, EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR);
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} else {
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Address = EFI_PCI_ADDRESS (Bus, Device, Func, PCI_CAPBILITY_POINTER_OFFSET);
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}
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//
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// Do not get byte read directly, because some PCI card will return 0xFF
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// when perform PCI-Express byte read, while return correct 0x00
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// when perform PCI-Express dword read, or PCI dword read.
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//
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PciRootBridgeIo->Pci.Read (
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PciRootBridgeIo,
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EfiPciWidthUint32,
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Address,
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1,
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&Register
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);
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CapabilityPtr = (UINT8)Register;
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}
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while (CapabilityPtr > 0x3F) {
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//
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// Mask it to DWORD alignment per PCI spec
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//
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CapabilityPtr &= 0xFC;
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Address = EFI_PCI_ADDRESS (Bus, Device, Func, CapabilityPtr);
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PciRootBridgeIo->Pci.Read (
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PciRootBridgeIo,
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EfiPciWidthUint16,
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Address,
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1,
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&CapabilityEntry
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);
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CapabilityID = (UINT8) CapabilityEntry;
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if (CapabilityID == CapId) {
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*Offset = CapabilityPtr;
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if (NextRegBlock != NULL) {
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*NextRegBlock = (UINT8) (CapabilityEntry >> 8);
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}
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return EFI_SUCCESS;
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}
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CapabilityPtr = (UINT8) (CapabilityEntry >> 8);
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}
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return EFI_NOT_FOUND;
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}
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