94 lines
3.2 KiB
C
94 lines
3.2 KiB
C
/** @file
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Define the structure for communication between chipset layer and common
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platform layer.
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;******************************************************************************
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;* Copyright (c) 2012, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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#ifndef _COMMON_SMBIOS_MEMORY_H_
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#define _COMMON_SMBIOS_MEMORY_H_
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#include <IndustryStandard/SmBios.h>
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#ifndef MAX_SOCKETS
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#define MAX_SOCKETS 4
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#endif
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//
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// Maximum number of sides supported per DIMM
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//
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#ifndef MAX_SIDES
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#define MAX_SIDES 2
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#endif
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//
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// Maximum number of rows supported by the memory controller
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//
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#ifndef MAX_ROWS
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#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)
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#endif
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///
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/// Maximum number of DIMM sockets supported by each channel
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///
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#ifndef MAX_SLOTS
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#define MAX_SLOTS 2
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#endif
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//
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// MAX SPD data size
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//
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#define MAX_SPD_DATA_SIZE 0x100
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//
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// Define saving SPD data structure
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//
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typedef struct {
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UINT32 ModuleSN;
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UINT8 SmbusBufferData[MAX_SPD_DATA_SIZE];
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} SPD_DATA;
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typedef struct {
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SPD_DATA DimmData[MAX_SOCKETS];
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} SPD_SAVE_DATA;
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//
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// Row configuration data structure
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//
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typedef struct {
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EFI_PHYSICAL_ADDRESS BaseAddress; // Base address of Row
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UINT64 RowLength; // Size of Row in bytes
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} DDR_ROW_CONFIG;
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//
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// This structure is used to set some SMBIOS Type 17 information without SPD on platform such as On-board memory.
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// If SpdExist = FALSE, the other four member must fill-in the information according to On-board memory.
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//
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//typedef struct {
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// BOOLEAN SpdExist; ///< Memory information can get from SPD.(Default is TRUE)
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// UINT8 MemoryType; ///< The enumeration value from MEMORY_DEVICE_TYPE. // The type of memory used in this device.(Offest 0x12)
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// MEMORY_DEVICE_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type.(Offest 0x13)
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// UINT16 TotalWidth; ///< The total width, in bits, of this memory device.(Offest 0x08)
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// UINT16 DataWidth; ///< The data width, in bits, of this memory device.(Offest 0x0A)
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//} H2O_MEMORY_ON_BOARD_INFO;
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typedef struct _H2O_SMBIOS_MEM_CONFIG_DATA {
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SMBIOS_TABLE_TYPE5 MemoryControllerInfo; // SmBios Type 5
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SMBIOS_TABLE_TYPE16 ArrayLocationData; // SmBios Type 16
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SMBIOS_TABLE_TYPE17 MemoryDeviceData; // SmBios Type 17
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SMBIOS_TABLE_TYPE18 Memory32bitErrorInfo; // SmBios Type 18
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BOOLEAN Interleaved; // Dual channel mode or Single channel mode
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DDR_ROW_CONFIG RowConfArray[MAX_ROWS]; // Row Configuration for all dimm
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// H2O_MEMORY_ON_BOARD_INFO MemoryOnBoardInfo; ///< MemoryOnBoardInfo is optional to fill-in.
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} H2O_SMBIOS_MEM_CONFIG_DATA;
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#endif
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