439 lines
22 KiB
C
439 lines
22 KiB
C
/** @file
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MMC 5.0 spec definition.
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;******************************************************************************
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;* Copyright (c) 2013 - 2016, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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#ifndef _MMC_H
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#define _MMC_H
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#pragma pack(1)
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#define CMD0 0
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#define CMD1 1
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#define CMD2 2
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#define CMD3 3
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#define CMD4 4
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#define CMD6 6
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#define CMD7 7
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#define CMD8 8
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#define CMD9 9
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#define CMD10 10
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#define CMD11 11
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#define CMD12 12
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#define CMD13 13
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#define CMD14 14
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#define CMD15 15
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#define CMD16 16
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#define CMD17 17
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#define CMD18 18
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#define CMD19 19
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#define CMD20 20
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#define CMD21 21
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#define CMD23 23
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#define CMD24 24
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#define CMD25 25
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#define CMD26 26
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#define CMD27 27
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#define CMD28 28
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#define CMD29 29
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#define CMD30 30
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#define CMD31 31
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#define CMD35 35
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#define CMD36 36
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#define CMD38 38
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#define CMD39 39
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#define CMD40 40
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#define CMD42 42
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#define CMD55 55
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#define CMD56 56
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//
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// MMC commands definition
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//
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#define CMD6_ACS_CMD_SET 0
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#define CMD6_ACS_SET_BIT 1
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#define CMD6_ACS_CLR_BIT 2
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#define CMD6_ACS_WR_BYTE 3
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#define FREQUENCY_OD (400 * 1000)
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#define FREQUENCY_MMC_PP (26 * 1000 * 1000)
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#define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000)
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#define FREQUENCY_MMC_PP_HIGH_200 (200 * 1000 * 1000)
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#define EXT_CSD_CARD_TYPE_MASK 0xFF // Mask out reserved bits
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#define EXT_CSD_CARD_TYPE_26 (1 << 0) // Card can run at 26MHz
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#define EXT_CSD_CARD_TYPE_52 (1 << 1) // Card can run at 52MHz
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#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) // Card can run at 52MHz, DDR mode @1.8V or 3V I/O
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#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) // Card can run at 52MHz, DDR mode @1.2V I/O
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#define EXT_CSD_CARD_TYPE_HS200_SDR_1_8V (1 << 4) // Card can run at 200MHz, SDR mode @1.8V I/O
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#define EXT_CSD_CARD_TYPE_HS200_SDR_1_2V (1 << 5) // Card can run at 200MHz, SDR mode @1.2V I/O
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#define EXT_CSD_CARD_TYPE_HS200_DDR_1_8V (1 << 6) // Card can run at 200MHz, DDR mode @1.8V I/O
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#define EXT_CSD_CARD_TYPE_HS200_DDR_1_2V (1 << 7) // Card can run at 200MHz, DDR mode @1.2V I/O
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#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V | EXT_CSD_CARD_TYPE_DDR_1_2V)
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#define EXT_CSD_CARD_TYPE_SDR_200 (EXT_CSD_CARD_TYPE_HS200_SDR_1_8V | EXT_CSD_CARD_TYPE_HS200_SDR_1_2V)
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#define EXT_CSD_CARD_TYPE_DDR_200 (EXT_CSD_CARD_TYPE_HS200_DDR_1_8V | EXT_CSD_CARD_TYPE_HS200_DDR_1_2V)
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#define DEFAULT_DSR_VALUE 0x404
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#define IDLE_STATE 0
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#define READY_STATE 1
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#define IDENT_STATE 2
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#define STBY_STATE 3
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#define TRAN_STATE 4
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#define DATA_STATE 5
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#define RCV_STATE 6
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#define PRG_STATE 7
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#define DIS_STATE 8
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#define BTST_STATE 9
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#define BYTE_MODE 0
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#define SECTOR_MODE 2
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//
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// 5.0 FFU
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//
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#define NORMAL_MODE 0
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#define FFU_MODE 1
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#define VENDOR_SPECIFIC_MODE 0x10
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#define FFU_INSTALL 1
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#define FFU_ABORT 2
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//
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// ExtCSD[173] BOOT_WP
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//
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#define B_PWR_WP_EN 0x01
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#define B_PERM_WP_EN 0x04
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#define B_WP_SEL_EN 0x80
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//
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// ExtCSD[173] BOOT_WP
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//
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#define BP1WP_PWRON 0x01
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#define BP2WP_PWRON 0x03
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//
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// ExtCSD[174] BOOT_WP_STATUS
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//
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#define BP1WP_STS_MASK 0x03
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#define BP2WP_STS_MASK 0x0C
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#define BP1WP_STS_PWRON 0x01
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#define BP1WP_STS_PERM 0x02
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#define BP2WP_STS_PWRON 0x04
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#define BP2WP_STS_PERM 0x08
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//
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// ExtCSD[175] ERASE_GROUP_DEF
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//
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#define USE_HIGH_CAP_ERASE_UNIT_SIZE (1 << 0)
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//
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// ExtCSD[192] EXT_CSD_REV
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//
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#define REV_4_1 1
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#define REV_4_41 5
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#define REV_4_5 6
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#define REV_5_0 7
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typedef struct {
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UINT32 Reserved1 :7; // 0 [6:0]
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UINT32 V1p65 :1; // 1.65V-1.95V [7:7]
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UINT32 V2p0 :7; // 2.00V-2.60V [14:8]
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UINT32 V2p7 :9; // 2.70V-3.60V [23:15]
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UINT32 Reserved2 :5; // Reserved [30:24]
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UINT32 AccessMode :2; // Access mode [30:29]
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UINT32 CardBusy :1; // This bit is set to LOW if the card has not finished the power up routine [31:31]
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} MMC_OCR;
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typedef struct {
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UINT8 NotUsed :1; // 1 [0:0]
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UINT8 Checksum :7; // CRC7 checksum [7:1]
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UINT8 ManufacturingDate; // Manufacturing date [15:8]
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UINT32 ProductSerialNumber; // Product serial number [47:16]
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UINT8 ProductRevision; // Product revision [55:48]
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UINT8 ProductName[6]; // Product name [103:56]
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UINT8 OemApplicationId; // OEM/Application ID [111:104]
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UINT8 CardBGA :2; // [113:112]
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UINT8 Reserved1 :6; // Reserved [119:114]
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UINT8 ManufacturerId; // Manufacturer ID [127:120]
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} MMC_CID;
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typedef struct {
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UINT8 NotUsed :1; // Not used, always 1 [0:0]
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UINT8 CRC :7; // CRC [7:1]
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UINT8 ECC :2; // ECC Code [9:8]
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UINT8 FileFormat :2; // File format [11:10]
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UINT8 TemporaryWriteProtect :1; // Temporary write protection [12:12]
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UINT8 PermanentWriteProtect :1; // Permanent write protection [13:13]
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UINT8 CopyFlag :1; // Copy flag (OTP) [14:14]
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UINT8 FileFormatGroup :1; // File format group [15:15]
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UINT16 ContentProtectApp :1; // Content Protection Application [16:16]
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UINT16 Reserved :4; // Reserved [20:17]
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UINT16 WriteBlkPartial :1; // Partial blocks for write allowed [21:21]
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UINT16 MaxWriteBlkLen :4; // Max. write data block length [25:22]
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UINT16 WriteSpeedFactor :3; // Write speed factor [28:26]
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UINT16 DefaultECC :2; // Manufacturer default ECC [30:29]
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UINT16 WriteProtectGroupEnable :1; // Write protect group enable [31:31]
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UINT32 WriteProtectGroupSize :5; // Write protect group size [36:32]
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UINT32 EraseGroupSizeMult :5; // Erase group size multiplier [41:37]
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UINT32 EraseGroupSize :5; // Erase group size [46:42]
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UINT32 DeviceSizeMult :3; // Device size multiplier [49:47]
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UINT32 VddMaxWriteCurrent :3; // Max. write current @ VDD max [52:50]
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UINT32 VddMinWriteCurrent :3; // Max. write current @ VDD min [55:53]
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UINT32 VddMaxReadCurrent :3; // Max. read current @ VDD max [58:56]
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UINT32 VddMinReadCurrent :3; // Max. read current @ VDD min [61:59]
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UINT32 DeviceSizeLow2 :2; // Device size [63:62]
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UINT32 DeviceSizeHigh10 :10;// Device size [73:64]
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UINT32 Reserved3 :2; // Reserved [75:74]
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UINT32 DSRImplemented :1; // DSR implemented [76:76]
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UINT32 ReadBlkMisalign :1; // Read block misalignment [77:77]
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UINT32 WriteBlkMisalign :1; // Write block misalignment [78:78]
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UINT32 ReadBlkPartial :1; // Partial blocks for read allowed [79:79]
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UINT32 MaxReadBlkLen :4; // Max. read data block length [83:80]
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UINT32 CardCommandClasses :12;// Card command classes [95:84]
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UINT8 MaxTransferRate; // Max. bus clock frequency [103:96]
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UINT8 Nsac; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
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UINT8 Taac; // Data read access-time 1 [119:112]
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UINT8 Reserved4 :2; // Reserved [121:120]
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UINT8 SpecVersion :4; // Specification version [125:122]
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UINT8 CsdStructure :2; // CSD structure [127:126]
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} MMC_CSD;
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typedef struct {
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//
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// Modes Segment
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//
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UINT8 Reserved133_0[16]; // Reserved [15:0]
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UINT8 SecureRemovalType; // Secure Removal Type [16:16]
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UINT8 ProdStateAwarenessEnablement; // Product state awareness enablement [17:17]
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UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size [21:18]
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UINT8 PreLoadingDataSize[4]; // Pre loading data size [25:22]
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UINT8 FfuStatus; // FFU status [26:26]
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UINT8 Reserved28_27[2]; // Reserved [28:27]
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UINT8 ModeOperationCodes; // Mode operation codes [29:29]
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UINT8 ModeConfig; // Mode config [30:30]
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UINT8 Reserved31; // Reserved [31:31]
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UINT8 FlushCache; // Flushing of the cache [32:32]
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UINT8 CacheCtrl; // Control to turn the Cache ON/OFF [33:33]
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UINT8 PowerOffNotification; // Power Off Notification [34:34]
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UINT8 PackedFailureIndex; // Packed command failure index [35:35]
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UINT8 PackedCommandStatus; // Packed command status [36:36]
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UINT8 ContextConf[15]; // Context configuration [51:37]
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UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute [53:52]
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UINT8 ExceptionEventsStatus[2]; // Exception events status [55:54]
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UINT8 ExceptionEventsCtrl[2]; // Exception events control [57:56]
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UINT8 DyncapNeeded; // Number of addressed group to be Released [58:58]
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UINT8 Class6Ctrl; // Class 6 commands control [59:59]
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UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation [60:60]
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UINT8 DataSectorSize; // Sector size [61:61]
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UINT8 UseNativeSector; // Sector size emulation [62:62]
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UINT8 NativeSectorSize; // Native sector size [63:63]
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UINT8 VendorSpecificField[64]; // Vendor Specific Fields [127:64]
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UINT8 Reserved129_128[2]; // Reserved [129:128]
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UINT8 ProgCidCsdDdrSupport; // Program CID/CSD in DDR mode support [130:130]
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UINT8 PeriodicWakeup; // Periodic Wake-up [131:131]
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UINT8 TcaseSupport; // Package Case Temperature is controlled [132:132]
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UINT8 ProdStateAwareness; // Production state awareness [133:133]
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UINT8 SecBadBlkMgmnt; // Bad Block Management mode [134]
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UINT8 Reserved135; // Reserved [135]
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UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address [139:136]
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UINT8 EnhSizeMul[3]; // Enhanced User Data Start Size [142:140]
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UINT8 GpSizeMul1[3]; // GPP1 Size [145:143]
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UINT8 GpSizeMul2[3]; // GPP2 Size [148:146]
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UINT8 GpSizeMul3[3]; // GPP3 Size [151:149]
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UINT8 GpSizeMul4[3]; // GPP4 Size [154:152]
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UINT8 PartitionSetCompleted; // Partitioning Setting [155]
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UINT8 PartitionAttributes; // Partitions attributes [156]
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UINT8 MaxEnhSizeMul[3]; // GPP4 Start Size [159:157]
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UINT8 PartitionSupport; // Partitioning Support [160]
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UINT8 HpiMgmt; // HPI management [161]
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UINT8 RstFun; // H/W reset function [162]
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UINT8 BkOpEn; // Enable background operations handshake [163]
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UINT8 BkOpStart; // Manually start background operations [164]
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UINT8 SanitizeStart; // Start Sanitize operation [165:165]
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UINT8 WrRelParam; // Write reliability parameter register [166]
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UINT8 WrRelSet; // Write reliability setting register [167]
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UINT8 RpmbSizeMul; // RPMB Size [168]
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UINT8 FwCfg; // FW configuration [169]
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UINT8 Reserved170; // Reserved [170]
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UINT8 UserWp; // User area write protection [171]
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UINT8 Reserved172; // Reserved [172]
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UINT8 BootWp; // Boot area write protection [173]
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UINT8 BootWpStatus; // Boot write protection status registers [174]
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UINT8 EraGroupDef; // High density erase group definition [175]
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UINT8 Reserved176; // Reserved [176]
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UINT8 BootBusWidth; // Boot bus width [177]
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UINT8 BootCfgProtect; // Boot config protection [178]
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UINT8 PartitionCfg; // Partition config [179]
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UINT8 Reserved180; // Reserved [180]
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UINT8 EraMemContent; // Erased Memory Content [181]
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UINT8 Reserved182; // Reserved [182]
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UINT8 BusWidth; // Bus Width Mode [183:183]
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UINT8 Reserved2; // Reserved [184:184]
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UINT8 HighSpeedTiming; // High Speed Interface Timing [185:185]
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UINT8 Reserved3; // Reserved [186:186]
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UINT8 PowerClass; // PowerClass [187:187]
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UINT8 Reserved4; // Reserved [188:188]
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UINT8 CmdSetRev; // Command Set Revision [189:189]
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UINT8 Reserved5; // Reserved [190:190]
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UINT8 CmdSet; // Command Set [191:191]
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//
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// Properties Segment
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//
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UINT8 ExtCsdRev; // Extended CSD Revision [192:192]
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UINT8 Reserved6; // Reserved [193:193]
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UINT8 CsdVer; // CSD Structure Version [194:194]
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UINT8 Reserved7; // Reserved [195:195]
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UINT8 DeviceType; // Device Type [196:196]
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UINT8 DriverStrength; // I/O Driver Strength [197:197]
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UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing [198:198]
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UINT8 PartitionSwitchTime; // Partition switching timing [199:199]
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UINT8 PwrClass52Mhz195; // Power Class for 52MHz @ 1.95V [200:200]
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UINT8 PwrClass26Mhz195V; // Power Class for 26MHz @ 1.95V [201:201]
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UINT8 PwrClass52Mhz360V; // Power Class for 52MHz @ 3.60V [202:202]
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UINT8 PwrClass26Mhz360V; // Power Class for 26MHz @ 3.60V [203:203]
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UINT8 Reserved8; // Reserved [204:204]
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UINT8 MinPerfR4B26Mhz; // Minimum Read Performance for 4bit @ 26 MHz [205:205]
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UINT8 MinPerfW4B26Mhz; // Minimum Write Performance for 4bit @ 26 MHz [206:206]
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UINT8 MinPerfR8B26Mhz4B52Mhz; // Minimum Read Performance for 8bit @ 26 MHz / 4bit @52MHz [207:207]
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UINT8 MinPerfW8B26Mhz4B52Mhz; // Minimum Write Performance for 8bit @ 26 MHz / 4bit @52MHz [208:208]
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UINT8 MinPerfR8B52Mhz; // Minimum Read Performance for 8bit @ 52 MHz [209:209]
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UINT8 MinPerfW8B52Mhz; // Minimum Write Performance for 8bit @ 52 MHz [210:210]
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UINT8 Reserved211; // Reserved [211]
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UINT8 SecCnt[4]; // Sector Count [215:212]
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UINT8 SlpNotificationTime; // Sleep Notification Timout [216]
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UINT8 SlpAwkTimeout; // Sleep/awake timeout [217]
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UINT8 ProdStateAwarenessTimeout; // Production state awareness timeout [218]
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UINT8 SlpCurrentVccq; // Sleep current (VCCQ) [219]
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UINT8 SlpCurrentVcq; // Sleep current (VCC) [220]
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UINT8 HcWpGrpSize; // High-capacity write protect group size [221]
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UINT8 RelWrSecCnt; // Reliable write sector count [222]
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UINT8 EraTimeoutMul; // High-capacity erase timeout [223]
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UINT8 HcEraGrpSize; // High-capacity erase unit size [224]
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UINT8 AccSize; // Access size [225]
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UINT8 BootSizeMul; // Boot partition size [226]
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UINT8 Reserved227; // Reserved [227]
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UINT8 BootInfo; // Boot information [228]
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UINT8 SecTrimMul; // Secure TRIM Multiplier [229]
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UINT8 SecEraMul; // Secure Erase Multiplier [230]
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UINT8 SecFeatureSupport; // Secure Feature support [231]
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UINT8 TrimMul; // TRIM Multiplier [232]
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UINT8 Reserved233; // Reserved [233]
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UINT8 MinPerfWDdrR8B52MHz; // [Min Read Performance for 8-bit @ 52MHz 234]
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UINT8 MinPerfDdrW8B52MHz; // Min Write Performance for 8-bit @ 52MHz [235]
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UINT8 PwrCl200_130; // Power class for 200MHz at VCCQ =1.3V, VCC = 3.6V [236]
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UINT8 PwrCl200_195; // Power class for 200MHz at VCCQ =1.95V, VCC = 3.6V [237]
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UINT8 PwrClDdr52Mhz195V; // Power class for 52MHz, DDR at 1.95V [238]
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UINT8 PwrClDdr52Mhz360V; // Power class for 52MHz, DDR at 3.6V [239]
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UINT8 Reserved240; // Reserved [240]
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UINT8 IniTimeOutAp; // 1st initialization time after partitioning [241]
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UINT8 CorrectPrgSecNum[4]; // Number of correctly programmed sectors [245:242]
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UINT8 BkOpStatus; // Background operations status [246:246]
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UINT8 PowerOffLongTime; // Power off notification(long) timeout [247:247]
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UINT8 GenericCmd6Time; // Generic CMD6 timeout [248:248]
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UINT8 CacheSize[4]; // Cache size [252:249]
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UINT8 PwrClDdr200_360; // Power class for 200MHz, DDR at VCC= 3.6V [253:253]
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UINT8 FirmwareVersion[8]; // Firmware version [261:254]
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UINT8 DeviceVersion[2]; // Device version [263:262]
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UINT8 OptimalTrimUnitSize; // Optimal trim unit size [264:264]
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UINT8 OptimalWriteSize; // Optimal write size [265:265]
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UINT8 OptimalReadSize; // Optimal read size [266:266]
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UINT8 PreEolInfo; // Pre EOL information [267:267]
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UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268:268]
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UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269:269]
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UINT8 VendorPtyHealthReport[32]; // Vendor proprietary health report [301:270]
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UINT8 NumOfFwSectorCorrectlyProgrammed[4]; // Number of FW sectors correctly programmed [305:302]
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UINT8 Reserved9[181]; // Reserved [486:306]
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UINT8 FfuArg[4]; // FFU Argument [490:487]
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UINT8 OperationCodeTimeout; // Operation codes timeout [491:491]
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UINT8 FfuFeatures; // FFU features [492:492]
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UINT8 SupportedModes; // Supported modes [493:493]
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UINT8 ExtSupport; // Extended partitions attribute support [494:494]
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UINT8 LargeUnitSizeM1; // Large Unit size [495:495]
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UINT8 ContextCapabilities; // Context management capabilities [496:496]
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UINT8 TagResSize; // Tag Resources Size [497:497]
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UINT8 TagUnitSize; // Tag Unit Size [498:498]
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UINT8 DataTagSupport; // Data Tag Support [499:499]
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UINT8 MaxPackedWrites; // Max packed write commands [500:500]
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UINT8 MaxPackedReads; // Max packed read commands [501:501]
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UINT8 BkOpSupport; // Background operations support [502:502]
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UINT8 HpiFeatures; // HPI features [503:503]
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UINT8 SupportCmdSet; // Supported Command Sets [504:504]
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UINT8 ExtSecCmdErr; // Extended Security Commands Error [505:505]
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UINT8 Reserved10[6]; // Reserved [511:506]
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} MMC_EXT_CSD;
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//
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// MMC Card Status definition
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//
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|
typedef struct {
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|
UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode
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UINT32 Reserved1: 2; //Reserved for Application Specific commands
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UINT32 Reserved2: 1; //
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|
UINT32 SappCmd: 1; //
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|
UINT32 Reserved3: 1; //Reserved
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|
UINT32 SwitchError: 1; //
|
|
UINT32 ReadyForData: 1; //
|
|
UINT32 CurrentState: 4; //
|
|
UINT32 EraRest: 1; //
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|
UINT32 Reserved4: 1; //Reserved
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|
UINT32 WpEraSkip: 1; //
|
|
UINT32 CidCsdOverWr: 1; //
|
|
UINT32 OverRun: 1; //
|
|
UINT32 UnderRun: 1; //
|
|
UINT32 Error: 1; //
|
|
UINT32 CcError: 1; //
|
|
UINT32 CardEccFailed: 1; //
|
|
UINT32 IllCmd: 1; //
|
|
UINT32 ComCrcError: 1; //
|
|
UINT32 LockUnLockFailed: 1; //
|
|
UINT32 CardIsLocked: 1; //
|
|
UINT32 WpViolation: 1; //
|
|
UINT32 EraParam: 1; //
|
|
UINT32 EraSeqError: 1; //
|
|
UINT32 BlkLenError: 1; //
|
|
UINT32 AddrMisalign: 1; //
|
|
UINT32 AddrOutOfRange: 1; //
|
|
}CARD_STATUS;
|
|
|
|
//
|
|
// Command Arguments
|
|
//
|
|
typedef union {
|
|
struct {
|
|
UINT8 CmdSet :3; // Command Set [2:0]
|
|
UINT8 Reserved1 :5; // Reserved [7:3]
|
|
UINT8 Value; // Value [15:8]
|
|
UINT8 Index; // Index [23:16]
|
|
UINT8 Access :2; // Access mode [25:24]
|
|
UINT8 Reserved2 :6; // Reserved [31:26]
|
|
} Bit;
|
|
UINT32 Value;
|
|
} CMD6_ARG;
|
|
|
|
//
|
|
// CMD42, device lock/unlock operation
|
|
//
|
|
typedef union {
|
|
struct {
|
|
UINT8 SetPwd :1; // Set new password to PWD [0:0]
|
|
UINT8 ClrPwd :1; // Clears PWD [1:1]
|
|
UINT8 Lock :1; // 1 = Locks the Device. 0 = Unlock the Device [2:2]
|
|
UINT8 Erase :1; // 1 Defines Forced Erase Operation [3:3]
|
|
UINT8 Reserved :4; // Reserved [4:7]
|
|
UINT8 PwdLen;
|
|
} Bit;
|
|
UINT16 Value;
|
|
} LOCK_UNLOCK_DATA_STRUCTURE;
|
|
|
|
#pragma pack()
|
|
#endif
|