221 lines
15 KiB
C
221 lines
15 KiB
C
/** @file
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Post code definitions
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;******************************************************************************
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;* Copyright (c) 2012 - 2021, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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#ifndef _POSTCODE_H_
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#define _POSTCODE_H_
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#include <Library/PostCodeLib.h>
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//
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// Use POST_CODE(Value) to display post code
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//
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//
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// SEC Functionality
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//
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#define SEC_SYSTEM_POWER_ON 0x01 // CPU power on and switch to Protected mode
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#define SEC_BEFORE_MICROCODE_PATCH 0x02 // Patching CPU microcode
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#define SEC_AFTER_MICROCODE_PATCH 0x03 // Setup Cache as RAM
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#define SEC_ACCESS_CSR 0x04 // PCIE MMIO Base Address initial
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#define SEC_GENERIC_MSRINIT 0x05 // CPU Generic MSR initial
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#define SEC_CPU_SPEEDCFG 0x06 // Setup CPU speed
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#define SEC_SETUP_CAR_OK 0x07 // Cache as RAM test
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#define SEC_FORCE_MAX_RATIO 0x08 // Tune CPU frequency ratio to maximum level
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#define SEC_GO_TO_SECSTARTUP 0x09 // Setup BIOS ROM cache
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#define SEC_GO_TO_PEICORE 0x0A // Enter Boot Firmware Volume
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//
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// PEI Functionality
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//
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#define PEI_SIO_INIT 0x70 // Super I/O initial
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#define PEI_CPU_REG_INIT 0x71 // CPU Early Initial
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#define PEI_CPU_AP_INIT 0x72 // Multi-processor Early initial
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#define PEI_CPU_HT_RESET 0x73 // HyperTransport initial
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#define PEI_PCIE_MMIO_INIT 0x74 // PCIE MMIO BAR Initial
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#define PEI_NB_REG_INIT 0x75 // North Bridge Early Initial
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#define PEI_SB_REG_INIT 0x76 // South Bridge Early Initial
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#define PEI_PCIE_TRAINING 0x77 // PCIE Training
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#define PEI_TPM_INIT 0x78 // TPM Initial
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#define PEI_SMBUS_INIT 0x79 // SMBUS Early Initial
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#define PEI_PROGRAM_CLOCK_GEN 0x7A // Clock Generator Initial
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#define PEI_IGD_EARLY_INITIAL 0x7B // Internal Graphic device early initial, PEI_IGDOpRegion
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#define PEI_HECI_INIT 0x7C // HECI Initial
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#define PEI_WATCHDOG_INIT 0x7D // Watchdog timer initial
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#define PEI_MEMORY_INIT 0x7E // Memory Initial for Normal boot.
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#define PEI_MEMORY_INIT_FOR_CRISIS 0x7F // Memory Initial for Crisis Recovery
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#define PEI_MEMORY_INSTALL 0x80 // Simple Memory test
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#define PEI_TXTPEI 0x81 // TXT function early initial
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#define PEI_SWITCH_STACK 0x82 // Start to use Memory
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#define PEI_MEMORY_CALLBACK 0x83 // Set cache for physical memory
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#define PEI_ENTER_RECOVERY_MODE 0x84 // Recovery device initial
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#define PEI_RECOVERY_MEDIA_FOUND 0x85 // Found Recovery image
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#define PEI_RECOVERY_MEDIA_NOT_FOUND 0x86 // Recovery image not found
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#define PEI_RECOVERY_LOAD_FILE_DONE 0x87 // Load Recovery Image complete
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#define PEI_RECOVERY_START_FLASH 0x88 // Start Flash BIOS with Recovery image
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#define PEI_ENTER_DXEIPL 0x89 // Loading BIOS image to RAM
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#define PEI_FINDING_DXE_CORE 0x8A // Loading DXE core
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#define PEI_GO_TO_DXE_CORE 0x8B // Enter DXE core
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#define PEI_IFFS_TRANSITION_START 0x8C // iFFS Transition Start
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#define PEI_IFFS_TRANSITION_END 0x8D // iFFS Transition End
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#define PEI_BOARD_ID_SETUP_FAILED 0x8E // BoardId maybe not be declared in both [SkuIds] and SKUID_IDENTIFIER of Project.dsc
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//
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// DXE Functionality
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//
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#define DXE_TCGDXE 0x40 // TPM initial in DXE
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#define DXE_SB_SPI_INIT 0x41 // South bridge SPI initial
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#define DXE_CF9_RESET 0x42 // Setup Reset service, DXE_CF9Reset
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#define DXE_SB_SERIAL_GPIO_INIT 0x43 // South bridge Serial GPIO initial, DXE_SB_SerialGPIO_INIT
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#define DXE_SMMACCESS 0x44 // Setup SMM ACCESS service
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#define DXE_NB_INIT 0x45 // North bridge Middle initial
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#define DXE_SIO_INIT 0x46 // Super I/O DXE initial
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#define DXE_LEGACY_REGION 0x47 // Setup Legacy Region service, DXE_LegacyRegion
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#define DXE_SB_INIT 0x48 // South Bridge Middle Initial
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#define DXE_IDENTIFY_FLASH_DEVICE 0x49 // Identify Flash device
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#define DXE_FTW_INIT 0x4A // Fault Tolerant Write verification
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#define DXE_VARIABLE_INIT 0x4B // Variable Service Initial
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#define DXE_VARIABLE_INIT_FAIL 0x4C // Fail to initial Variable Service
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#define DXE_MTC_INIT 0x4D // MTC Initial
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#define DXE_CPU_INIT 0x4E // CPU Middle Initial
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#define DXE_MP_CPU_INIT 0x4F // Multi-processor Middle Initial
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#define DXE_SMBUS_INIT 0x50 // SMBUS Driver Initial
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#define DXE_SMART_TIMER_INIT 0x51 // 8259 Initial
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#define DXE_PCRTC_INIT 0x52 // RTC Initial
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#define DXE_SATA_INIT 0x53 // SATA Controller early initial
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#define DXE_SMM_CONTROLER_INIT 0x54 // Setup SMM Control service, DXE_SMMControler_INIT
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#define DXE_LEGACY_INTERRUPT 0x55 // Setup Legacy Interruput service, DXE_LegacyInterrupt
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#define DXE_RELOCATE_SMBASE 0x56 // Relocate SMM BASE
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#define DXE_FIRST_SMI 0x57 // SMI test
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#define DXE_VTD_INIT 0x58 // VTD Initial
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#define DXE_BEFORE_CSM16_INIT 0x59 // Legacy BIOS initial
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#define DXE_AFTER_CSM16_INIT 0x5A // Legacy interrupt function initial
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#define DXE_LOAD_ACPI_TABLE 0x5B // ACPI Table Initial
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#define DXE_SB_DISPATCH 0x5C // Setup SB SMM Dispatcher service, DXE_SB_Dispatch
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#define DXE_SB_IOTRAP_INIT 0x5D // Setup SB IOTRAP Service
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#define DXE_SUBCLASS_DRIVER 0x5E // Build AMT Table
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#define DXE_PPM_INIT 0x5F // PPM Initial
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#define DXE_HECIDRV_INIT 0x60 // HECIDRV Initial
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#define DXE_VARIABLE_RECLAIM 0x61 // Variable store garbage collection and reclaim operation
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#define DXE_FLASH_PART_NONSUPPORT 0x62 // Do not support flash part (which is defined in SpiDevice.c)
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#define DXE_FAULT_TOLERANCE_FCHECK_FAILED 0x63 // Platform does not comply with the BIOS update fault tolerance requirement.
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//
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// BDS Functionality
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//
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#define BDS_ENTER_BDS 0x10 // Enter BDS entry
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#define BDS_INSTALL_HOTKEY 0x11 // Install Hotkey service
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#define BDS_ASF_INIT 0x12 // ASF Initial
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#define BDS_PCI_ENUMERATION_START 0x13 // PCI enumeration
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#define BDS_BEFORE_PCIIO_INSTALL 0x14 // PCI resource assign complete
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#define BDS_PCI_ENUMERATION_END 0x15 // PCI enumeration complete
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#define BDS_CONNECT_CONSOLE_IN 0x16 // Keyboard Controller, Keyboard and Moust initial
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#define BDS_CONNECT_CONSOLE_OUT 0x17 // Video device initial
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#define BDS_CONNECT_STD_ERR 0x18 // Error report device initial
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#define BDS_CONNECT_USB_HC 0x19 // USB host controller initial
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#define BDS_CONNECT_USB_BUS 0x1A // USB BUS driver initial
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#define BDS_CONNECT_USB_DEVICE 0x1B // USB device driver initial
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#define BDS_NO_CONSOLE_ACTION 0x1C // Console device initial fail
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#define BDS_DISPLAY_LOGO_SYSTEM_INFO 0x1D // Display logo or system information
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#define BDS_START_IDE_CONTROLLER 0x1E // IDE controller initial
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#define BDS_START_SATA_CONTROLLER 0x1F // SATA controller initial
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#define BDS_START_ISA_ACPI_CONTROLLER 0x20 // SIO controller initial
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#define BDS_START_ISA_BUS 0x21 // ISA BUS driver initial
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#define BDS_START_ISA_FDD 0x22 // Floppy device initial
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#define BDS_START_ISA_SEIRAL 0x23 // Serial device initial
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#define BDS_START_IDE_BUS 0x24 // IDE device initial
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#define BDS_START_AHCI_BUS 0x25 // AHCI device initial
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#define BDS_CONNECT_LEGACY_ROM 0x26 // Dispatch option ROMs
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#define BDS_ENUMERATE_ALL_BOOT_OPTION 0x27 // Get boot device information
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#define BDS_END_OF_BOOT_SELECTION 0x28 // End of boot selection
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#define BDS_ENTER_SETUP 0x29 // Enter Setup Menu
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#define BDS_ENTER_BOOT_MANAGER 0x2A // Enter Boot manager
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#define BDS_BOOT_DEVICE_SELECT 0x2B // Try to boot system to OS
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#define BDS_EFI64_SHADOW_ALL_LEGACY_ROM 0x2C // Shadow Misc Option ROM
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#define BDS_ACPI_S3SAVE 0x2D // Save S3 resume required data in RAM
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#define BDS_READY_TO_BOOT_EVENT 0x2E // Last Chipset initial before boot to OS
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#define BDS_GO_LEGACY_BOOT 0x2F // Start to boot Legacy OS
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#define BDS_GO_UEFI_BOOT 0x30 // Start to boot UEFI OS
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#define BDS_LEGACY16_PREPARE_TO_BOOT 0x31 // Prepare to Boot to Legacy OS
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#define BDS_EXIT_BOOT_SERVICES 0x32 // Send END of POST Message to ME via HECI
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#define BDS_LEGACY_BOOT_EVENT 0x33 // Last Chipset initial before boot to Legacy OS.
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#define BDS_ENTER_LEGACY_16_BOOT 0x34 // Ready to Boot Legacy OS.
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#define BDS_RECOVERY_START_FLASH 0x35 // Fast recovery start flash
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#define BDS_START_SDHC_BUS 0x36 // SDHC device initial
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#define BDS_CONNECT_ATA_LEGACY 0x37 // Ata Legacy device initial
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#define BDS_CONNECT_SD_LEGACY 0x38 // SD Legacy device initial
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#define BDS_ENTER_FIRMWARE_UI 0x39 // Enter firmware UI
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#define BDS_PLATFORM_RECOVERY 0x3A // Perform Platform-Defined boot option recovery
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#define BDS_OS_RECOVERY 0x3B // Perform OS-Defined boot option recovery
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#define BDS_SYSPREP 0x3C // Perform system preparation applications
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//
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// PostBDS Functionality
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//
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#define POST_BDS_NO_BOOT_DEVICE 0xF9 // No Boot Device, PostBDS_NO_BOOT_DEVICE
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#define POST_BDS_START_IMAGE 0xFB // UEFI Boot Start Image, PostBDS_START_IMAGE
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#define POST_BDS_ENTER_INT19 0xFD // Legacy 16 boot entry
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#define POST_BDS_JUMP_BOOT_SECTOR 0xFE // Try to Boot with INT 19
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//
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// SMM Functionality
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//
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#define SMM_IDENTIFY_FLASH_DEVICE 0xA0 // Identify Flash device in SMM
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#define SMM_SMM_PLATFORM_INIT 0xA2 // SMM service initial
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#define SMM_ACPI_ENABLE_START 0xA6 // OS call ACPI enable function
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#define SMM_ACPI_ENABLE_END 0xA7 // ACPI enable function complete
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#define SMM_S1_SLEEP_CALLBACK 0xA1 // Enter S1
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#define SMM_S3_SLEEP_CALLBACK 0xA3 // Enter S3
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#define SMM_S4_SLEEP_CALLBACK 0xA4 // Enter S4
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#define SMM_S5_SLEEP_CALLBACK 0xA5 // Enter S5
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#define SMM_ACPI_DISABLE_START 0xA8 // OS call ACPI disable function
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#define SMM_ACPI_DISABLE_END 0xA9 // ACPI disable function complete
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//
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// S3 Functionality
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//
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#define S3_RESTORE_MEMORY_CONTROLLER 0xC0 // Memory initial for S3 resume
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#define S3_INSTALL_S3_MEMORY 0xC1 // Get S3 resume required data from memory
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#define S3_SWITCH_STACK 0xC2 // Start to use memory during S3 resume
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#define S3_MEMORY_CALLBACK 0xC3 // Set cache for physical memory during S3 resume
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#define S3_ENTER_S3_RESUME_PEIM 0xC4 // Start to restore system configuration
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#define S3_BEFORE_ACPI_BOOT_SCRIPT 0xC5 // Restore system configuration stage 1
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#define S3_BEFORE_RUNTIME_BOOT_SCRIPT 0xC6 // Restore system configuration stage 2
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#define S3_BEFORE_RELOCATE_SMM_BASE 0xC7 // Relocate SMM BASE during S3 resume
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#define S3_BEFORE_MP_INIT 0xC8 // Multi-processor initial during S3 resume
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#define S3_BEFORE_RESTORE_ACPI_CALLBACK 0xC9 // Start to restore system configuration in SMM
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#define S3_AFTER_RESTORE_ACPI_CALLBACK 0xCA // Restore system configuration in SMM complete
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#define S3_GO_TO_FACS_WAKING_VECTOR 0xCB // Back to OS
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//
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// ASL Functionality
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//
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#define ASL_ENTER_S1 0x51 // Prepare to enter S1
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#define ASL_ENTER_S3 0x53 // Prepare to enter S3
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#define ASL_ENTER_S4 0x54 // Prepare to enter S4
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#define ASL_ENTER_S5 0x55 // Prepare to enter S5
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#define ASL_WAKEUP_S1 0xE1 // System wakeup from S1
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#define ASL_WAKEUP_S3 0xE3 // System wakeup from S3
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#define ASL_WAKEUP_S4 0xE4 // System wakeup from S4
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#define ASL_WAKEUP_S5 0xE5 // System wakeup from S5
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//
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// Platform Security
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//
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#define POST_COMPILER_ERROR 0xEC // Stack Frame Checks
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#define POST_CPU_GENERAL_PROTECTION_FAULT_EXCEPTION 0xED // General Protection Fault
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#define POST_CPU_PAGE_FAULT_EXCEPTION 0xEE // Page Fault
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#endif
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