1084 lines
32 KiB
C
1084 lines
32 KiB
C
/** @file
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XhcDebug.c
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;******************************************************************************
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;* Copyright (c) 2015, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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#include <Uefi.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PrintLib.h>
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#include <Library/PciLib.h>
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#include <Library/IoLib.h>
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#include <Library/TimerLib.h>
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#include <Library/PcdLib.h>
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#include <Library/BaseLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/HobLib.h>
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#include <Library/H2OLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Protocol/UsbIo.h>
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#include <XhcStatusCode.h>
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#include "Pci.h"
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STATIC DEBUG_IO_PRIVATE_DATA *mPrivate = NULL;
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STATIC EFI_GUID mXhcDebugHobGuid = { 0x850fae6a, 0x16da, 0x4b42, { 0x8d, 0x84, 0x3c, 0x36, 0x56, 0xb1, 0xe0, 0x1f } };
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STATIC UINT8 mStr0[0x10] = { 0x04, 0x03, 0x09, 0x04 };
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STATIC UINT8 mManufacturer[0x10] = { 0x0e, 0x03, 'I', 0x00, 'n', 0x00, 's', 0x00, 'y', 0x00, 'd', 0x00, 'e', 0x00 };
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STATIC UINT8 mProduct[0x30] = { 0x2a, 0x03, 'I', 0x00, 'n', 0x00, 's', 0x00, 'y', 0x00, 'd', 0x00, 'e', 0x00, ' ', 0x00,
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'U', 0x00, 'S', 0x00, 'B', 0x00, '3', 0x00, ' ', 0x00,
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'D', 0x00, 'e', 0x00, 'b', 0x00, 'u', 0x00, 'g', 0x00, 'g', 0x00, 'e', 0x00, 'r', 0x00 };
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STATIC UINT8 mSerialNum[0x10] = { 0x08, 0x03, '1', 0x00, '.', 0x00, '0', 0x00 };
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struct
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{
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CHAR8 Signature[4];
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DEBUGIO_CONFIG Config;
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UINT32 XhciBar;
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} XhcDebugIoConfig = {
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{ 'D', 'B', 'G', 'C' },
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{ 0, // 0:LPC, 1:PCI
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0, // 0:Bypass connection off, 1:Bypass connection on
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0, // 0:USB, 1:LPT, 2:COM
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FixedPcdGet8 (PcdUsbDebugXhciControl), // USB HC port
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0, // USB debug port
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0x0080, // Debug port
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10 // Bypass timeout
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},
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FixedPcdGet32 (PcdUsbDebugXhciBaseAddress)
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};
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UINT8
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EFIAPI
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ByteRotate (
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IN UINT8 Data
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)
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{
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return (Data << 4) | (Data >> 4);
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}
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//
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// Internal Functions
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//
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STATIC
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EFI_STATUS
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InitXhciDebugPort (
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IN UINT32 HcToken,
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OUT UINT32 *DbgBar,
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IN OUT UINT32 *DebugContextAddr,
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IN BOOLEAN RuntimeState
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);
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/**
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Is it USB Device
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@param [in] PciAddress
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@return 0x00 : No
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@return 0x01 : XHCI
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@return 0x0f : Pcie bridge
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**/
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STATIC
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UINTN
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IsUsbDevice (
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IN UINT32 PciAddress
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)
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{
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UINT32 ClassCode;
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PciRead (EfiWidthUint32, PciAddress + 0x08, &ClassCode);
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ClassCode &= 0xFFFFFF00;
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switch (ClassCode) {
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case 0x0C033000: return XHCI;
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case 0x06040000: return BRIDGE;
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}
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return 0;
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}
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/**
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Memory copy common routine
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@param [in] DestAddr Destination Address
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@param [in] SourAddr Source Address
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@param [in] Width Data width
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@retval EFI_SUCCESS Success
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@retval EFI_UNSUPPORTED Upsupported
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**/
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STATIC
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EFI_STATUS
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MemoryCopy (
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IN UINT8 *DestAddr,
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IN UINT8 *SourAddr,
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IN EFI_WIDTH Width
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)
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{
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switch (Width) {
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case EfiWidthUint32:
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*(UINT32*)DestAddr = *(UINT32*)SourAddr;
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break;
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case EfiWidthUint64:
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//
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// break down into two 32 bits operation
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//
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*(UINT32*)(DestAddr + 0) = *(UINT32*)(SourAddr + 0);
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*(UINT32*)(DestAddr + 4) = *(UINT32*)(SourAddr + 4);
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break;
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default:
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return EFI_UNSUPPORTED;
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}
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return EFI_SUCCESS;
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}
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/**
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Read Xhc debug register
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@param [in] Bar Debug capability base address
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@param [in] Width Data width
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@param [in] RegAddr
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@param [in, out] Data A pointer to data read from register
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@retval EFI_SUCCESS Success
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@retval EFI_UNSUPPORTED Upsupported
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**/
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EFI_STATUS
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ReadXhcDebugReg (
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IN UINT32 Bar,
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IN EFI_WIDTH Width,
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IN UINT32 RegAddr,
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IN OUT VOID *Data
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)
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{
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return MemoryCopy(Data, (UINT8*)(UINTN)(Bar + RegAddr), Width);
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}
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/**
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Write Xhc debug register
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@param [in] Bar Debug capability base address
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@param [in] Width Data width
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@param [in] RegAddr
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@param [in] Data A pointer to data write to register
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@retval EFI_SUCCESS Success
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@retval EFI_UNSUPPORTED Upsupported
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**/
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EFI_STATUS
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WriteXhcDebugReg (
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IN UINT32 Bar,
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IN EFI_WIDTH Width,
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IN UINT32 RegAddr,
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IN VOID *Data
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)
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{
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return MemoryCopy((UINT8*)(UINTN)(Bar + RegAddr), Data, Width);
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}
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/**
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Update the event dequeue pointer
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@param [in] DbgBar
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@param [in] DebugContext A pointer to debug context
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@param [in] TargetAddr
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**/
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STATIC
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BOOLEAN
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UpdateEventDequeuePointer (
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IN UINT32 DbgBar,
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IN DBG_CONTEXT *DebugContext,
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IN UINT64 TargetAddr
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)
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{
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UINT64 Data;
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UINT32 CycleBit;
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XHCI_TRANSFER_EVENT *Event;
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BOOLEAN Result = FALSE;
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ReadXhcDebugReg (DbgBar, EfiWidthUint64, XHCI_DCERDP, &Data);
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Event = (XHCI_TRANSFER_EVENT*)(UINTN)Data;
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CycleBit = Event->CycleBit;
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while (CycleBit == Event->CycleBit) {
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if (TargetAddr && TargetAddr == Event->TRBPointer) Result = TRUE;
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Event ++;
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if ((UINT64)(UINTN)Event >= DebugContext->EventRingSegmentTable.RingSegmentBaseAddress + (MultU64x32 (DebugContext->EventRingSegmentTable.RingSegmentSize, sizeof (XHCI_TRANSFER_EVENT)))) {
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Event = (XHCI_TRANSFER_EVENT*)(UINTN)DebugContext->EventRingSegmentTable.RingSegmentBaseAddress;
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CycleBit ^= 1;
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}
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}
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Data = (UINT64)(UINTN)Event;
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WriteXhcDebugReg (DbgBar, EfiWidthUint64, XHCI_DCERDP, &Data);
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do {
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ReadXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCST, &Data);
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} while (Data & B_DCST_ER);
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return Result;
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}
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/**
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Get USB Bar
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@param [in] HcToken
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@return USB BAR
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**/
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STATIC
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UINT32
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GetUsbBar (
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IN UINT32 HcToken
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)
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{
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UINT32 PciAddress;
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UINT32 BarAddress;
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PciAddress = EFI_PCI_ADDRESS(0, ((HcToken & B_TOKEN_XHCI_PCI_DEV) >> N_TOKEN_XHCI_PCI_DEV), ((HcToken & B_TOKEN_XHCI_PCI_FUN) >> N_TOKEN_XHCI_PCI_FUN), 0);
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if (IsUsbDevice (PciAddress) == BRIDGE) {
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PciRead (EfiWidthUint32, PciAddress + 0x18, &BarAddress);
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PciAddress = EFI_PCI_ADDRESS(((BarAddress >> 8) & 0xff), 0, 0, 0);
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}
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PciRead (EfiWidthUint32, PciAddress + 0x10, &BarAddress);
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BarAddress &= ~0x0f;
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if (BarAddress != 0) {
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if (BarAddress != XhcDebugIoConfig.XhciBar) {
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if ((*(UINT32*)(UINTN)BarAddress & 0xff000000) == 0x01000000 && (*(UINT32*)(UINTN)BarAddress & 0x000000ff) > 0) return BarAddress;
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} else return BarAddress;
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}
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PciWrite (EfiWidthUint32, PciAddress + 0x10, &XhcDebugIoConfig.XhciBar);
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return XhcDebugIoConfig.XhciBar;
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}
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/**
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Turn power state on
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@param [in] PciAddress
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**/
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STATIC
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VOID
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PowerStateOn (
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IN UINT32 PciAddress
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)
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{
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UINT32 Data;
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UINT8 CapPtr;
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//
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// Searching for Power Capabilities
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//
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PciRead (EfiWidthUint8, PciAddress + 0x34, &CapPtr);
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while (CapPtr != 0) {
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PciRead (EfiWidthUint32, PciAddress + CapPtr, &Data);
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if ((Data & 0xff) == 0x01) {
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PciRead (EfiWidthUint8, PciAddress + CapPtr + 4, &Data);
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if ((Data & 0x03) != 0) {
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Data = 0;
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PciWrite (EfiWidthUint8, PciAddress + CapPtr + 4, &Data);
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MicroSecondDelay (100000);
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}
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break;
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}
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CapPtr = (UINT8)((Data >> 8) & 0xff);
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}
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if (IsUsbDevice (PciAddress) == BRIDGE) {
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//
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// Set the power state for XHC device after bridge
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//
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PciRead (EfiWidthUint32, PciAddress + 0x18, &Data);
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PowerStateOn ((UINT32)EFI_PCI_ADDRESS(((Data >> 8) & 0xff), 0, 0, 0));
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}
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}
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/**
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Get Xhci PCI location
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@param [in] HcToken
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@return PCI address
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**/
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STATIC
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UINT32
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GetXhciLocation (
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IN UINT32 HcToken
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)
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{
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UINT32 PciAddress;
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UINT32 Bus;
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UINT32 BusEnd;
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UINT32 Data;
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UINT32 XhciBridge;
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BOOLEAN BusMasterResetNeeded;
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PciAddress = EFI_PCI_ADDRESS(0, ((HcToken & B_TOKEN_XHCI_PCI_DEV) >> N_TOKEN_XHCI_PCI_DEV), ((HcToken & B_TOKEN_XHCI_PCI_FUN) >> N_TOKEN_XHCI_PCI_FUN), 0);
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switch (IsUsbDevice (PciAddress)) {
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case XHCI:
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Data = 0;
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PciRead (EfiWidthUint16, PciAddress + 4, &Data);
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if ((Data & 0x06) != 0x06) {
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Data |= 0x06;
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PciWrite (EfiWidthUint16, PciAddress + 4, &Data);
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MicroSecondDelay (100000);
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}
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PowerStateOn (PciAddress);
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return PciAddress;
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case BRIDGE:
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BusMasterResetNeeded = FALSE;
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PciRead (EfiWidthUint16, PciAddress + 4, &Data);
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if ((Data & 0x06) != 0x06) {
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Data |= 0x06;
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PciWrite (EfiWidthUint16, PciAddress + 4, &Data);
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MicroSecondDelay (100000);
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BusMasterResetNeeded = TRUE;
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}
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PciRead (EfiWidthUint32, PciAddress + 0x18, &Data);
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if (Data == 0) {
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XhciBridge = (HcToken & B_TOKEN_XHCI_PCI_BRIDGE) >> N_TOKEN_XHCI_PCI_BRIDGE;
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Data = (XhciBridge << 16) + (XhciBridge << 8);
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PciWrite (EfiWidthUint32, PciAddress + 0x18, &Data);
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MicroSecondDelay (100000);
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BusMasterResetNeeded = TRUE;
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}
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PowerStateOn (PciAddress);
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Bus = (Data >> 8) & 0xff;
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BusEnd = (Data >> 16) & 0xff;
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for (; Bus <= BusEnd; Bus ++) {
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PciAddress = EFI_PCI_ADDRESS(Bus, 0, 0, 0);
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if ((IsUsbDevice (PciAddress)) == XHCI) {
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PciRead (EfiWidthUint16, PciAddress + 4, &Data);
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if (BusMasterResetNeeded || ((Data & 0x06) != 0x06)) {
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Data |= 0x06;
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PciWrite (EfiWidthUint16, PciAddress + 4, &Data);
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MicroSecondDelay (100000);
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}
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return PciAddress;
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}
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}
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}
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return 0;
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}
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/**
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Route the debug port from ordinary USB3 port
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@param [in] Bar
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**/
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STATIC
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VOID
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RouteDebugPort (
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IN UINT32 Bar
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)
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{
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UINTN Index;
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UINT32 Data;
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UINT32 *Port;
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UINTN Count;
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Index = ((*(UINT32*)(UINTN)(Bar + 0x10) & 0xffff0000) >> 14);
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do {
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Data = *(UINT32*)(UINTN)(Bar + Index);
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if ((Data & 0xff0000ff) == 0x3000002) {
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//
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// USB3 supported protocol
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//
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Data = *(UINT32*)(UINTN)(Bar + Index + 8);
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Port = (UINT32*)(UINTN)(Bar + 0x400 + (*(UINT32*)(UINTN)Bar & 0xff) + (((Data & 0xff) - 1) * 0x10));
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Count = (UINTN)((Data >> 8) & 0xff);
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for (Index = 0; Index < Count; Index ++, Port += 4) {
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Data = *Port;
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if ((Data & 0x1e0) == 0xc0) {
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//
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// The debug port found, toggle the port power to make the signal route to debug port
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//
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Data &= ~0x200;
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*Port = Data;
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MicroSecondDelay (500000);
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Data = 0x200;
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*Port = Data;
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MicroSecondDelay (500000);
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}
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}
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break;
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}
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Index += (UINTN)((Data & 0xff00) >> (8 - 2));
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} while ((Data & 0xff00) != 0);
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}
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/**
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Detect Xhci
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@param [in] Token
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@param [out] DbgBar
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@param [in, out] DebugContextAddr
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@retval EFI_SUCCESS
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@retval EFI_NOT_FOUND
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**/
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STATIC
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EFI_STATUS
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DetectXhci (
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IN UINT32 *Token,
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OUT UINT32 *DbgBar,
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IN OUT UINT32 *DebugContextAddr
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)
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{
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UINT32 PciAddress;
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UINT32 Dev;
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UINT32 Fun;
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UINT32 Data;
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UINT32 HcToken;
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UINTN HcPort;
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BOOLEAN Found;
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UINT32 Bridge;
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UINT32 Device;
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UINT32 Bar;
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UINT32 Index;
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UINT32 LmcIndex;
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UINT32 XhciBridge;
|
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if (*Token != 0) {
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//
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// Runtime checking
|
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//
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return InitXhciDebugPort(*Token, DbgBar, DebugContextAddr, TRUE);
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}
|
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//
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// XHCI detection
|
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//
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HcPort = XhcDebugIoConfig.Config.UsbHcPort;
|
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Bridge = 0;
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Device = 0;
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Found = FALSE;
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for (Dev = 0; Dev < 0x20 && !Found; Dev ++) {
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for (Fun = 0; Fun < 8 && !Found; Fun ++) {
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PciAddress = EFI_PCI_ADDRESS(0, Dev, Fun, 0);
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if (IsUsbDevice (PciAddress) == XHCI && HcPort -- == 0) {
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Device = PciAddress;
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Found = TRUE;
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}
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}
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}
|
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if (!Found) {
|
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if (!Bridge) {
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for (Dev = 0; Dev < 0x20 && !Found; Dev ++) {
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for (Fun = 0; Fun < 8 && !Found; Fun ++) {
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PciAddress = EFI_PCI_ADDRESS(0, Dev, Fun, 0);
|
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if ((IsUsbDevice (PciAddress)) == BRIDGE) {
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PciRead (EfiWidthUint32, PciAddress + 0x18, &Data);
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if (Data == 0) {
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XhciBridge = (XHCI_BRIDGE << 16) + (XHCI_BRIDGE << 8);
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PciWrite (EfiWidthUint32, PciAddress + 0x18, &XhciBridge);
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MicroSecondDelay (1000);
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XhciBridge = XHCI_BRIDGE;
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} else {
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XhciBridge = (Data >> 8) & 0xff;
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}
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Device = EFI_PCI_ADDRESS(XhciBridge, 0, 0, 0);
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if ((IsUsbDevice (Device)) == XHCI && HcPort -- == 0) {
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Bridge = EFI_PCI_ADDRESS(0, Dev, Fun, 0);
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Found = TRUE;
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} else if (Data == 0) {
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PciWrite (EfiWidthUint32, PciAddress + 0x18, &Data);
|
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MicroSecondDelay (10000);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
if (Bridge) {
|
|
PowerStateOn (Bridge);
|
|
if (IsUsbDevice (Device) != XHCI) return EFI_NOT_FOUND; else Found = TRUE;
|
|
Bar = GetUsbBar ((Bridge << 16) & 0xff000000);
|
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Data = (Bar & 0xfff00000) + ((Bar & 0xfff00000) >> 16);
|
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PciWrite (EfiWidthUint32, Bridge + 0x20, &Data);
|
|
MicroSecondDelay (1000);
|
|
}
|
|
}
|
|
if (Found) {
|
|
if (!Bridge) {
|
|
PciAddress = Device;
|
|
HcToken = (PciAddress << 16) & (B_TOKEN_XHCI_PCI_DEV | B_TOKEN_XHCI_PCI_FUN);
|
|
} else {
|
|
PciRead (EfiWidthUint32, Bridge + 0x18, &Data);
|
|
XhciBridge = (Data >> 8) & 0xff;
|
|
PciAddress = EFI_PCI_ADDRESS(XhciBridge, 0, 0, 0);
|
|
HcToken = ((Bridge << 16) & (B_TOKEN_XHCI_PCI_DEV | B_TOKEN_XHCI_PCI_FUN)) + ((XhciBridge << 16) & B_TOKEN_XHCI_PCI_BRIDGE);
|
|
PciRead (EfiWidthUint16, Bridge + 4, &Data);
|
|
Data |= 0x06;
|
|
PciWrite (EfiWidthUint16, Bridge + 4, &Data);
|
|
MicroSecondDelay (100000);
|
|
|
|
|
|
}
|
|
Bar = GetUsbBar (HcToken);
|
|
PowerStateOn (PciAddress);
|
|
PciRead (EfiWidthUint16, PciAddress + 4, &Data);
|
|
Data |= 0x06;
|
|
PciWrite (EfiWidthUint16, PciAddress + 4, &Data);
|
|
MicroSecondDelay (100000);
|
|
//
|
|
// Port routing detection for Intel XHCI
|
|
//
|
|
Data = 0;
|
|
PciRead (EfiWidthUint16, PciAddress, &Data);
|
|
if (Data == 0x8086) {
|
|
PciRead (EfiWidthUint32, PciAddress + 0xd8, &Dev);
|
|
Data = Dev ^ 0xffffffff;
|
|
PciWrite (EfiWidthUint32, PciAddress + 0xd8, &Data);
|
|
PciRead (EfiWidthUint32, PciAddress + 0xd8, &Data);
|
|
if (Data != Dev) {
|
|
HcToken |= B_TOKEN_PORT_ROUTING;
|
|
}
|
|
}
|
|
Index = ((*(UINT32*)(UINTN)(Bar + 0x10) & 0xffff0000) >> 14);
|
|
LmcIndex = 0;
|
|
do {
|
|
Data = *(UINT32*)(UINTN)(Bar + Index);
|
|
if ((Data & 0xff) == 0x0a) {
|
|
//
|
|
// Debug Capability
|
|
//
|
|
HcToken |= (Index & B_TOKEN_DEBUG_CAP_INDEX);
|
|
}
|
|
Index += ((Data & 0xff00) >> (8 - 2));
|
|
} while ((Data & 0xff00) != 0);
|
|
if ((HcToken & B_TOKEN_DEBUG_CAP_INDEX) != 0) {
|
|
*Token = HcToken;
|
|
return EFI_SUCCESS;
|
|
}
|
|
}
|
|
return EFI_NOT_FOUND;
|
|
}
|
|
|
|
/**
|
|
Debug Software Startup with Non-Initialized XHCI
|
|
|
|
@param [in] HcToken
|
|
@param [out] DebugBar
|
|
@param [in, out] DebugContextAddr
|
|
@param [in] RuntimeState
|
|
|
|
@retval EFI_SUCCESS
|
|
|
|
**/
|
|
STATIC
|
|
EFI_STATUS
|
|
InitXhciDebugPort(
|
|
IN UINT32 HcToken,
|
|
OUT UINT32 *DebugBar,
|
|
IN OUT UINT32 *DebugContextAddr,
|
|
IN BOOLEAN RuntimeState
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
UINT32 PciAddress;
|
|
UINT32 Bar;
|
|
UINT32 DbgBar;
|
|
UINT32 Data;
|
|
UINT64 Pointer;
|
|
DBG_CONTEXT *DebugContext;
|
|
UINT8 PostCode;
|
|
UINTN Index;
|
|
UINTN Timeout;
|
|
BOOLEAN UpdateContext;
|
|
|
|
UpdateContext = TRUE;
|
|
if ((PciAddress = GetXhciLocation (HcToken)) == 0) return EFI_DEVICE_ERROR;
|
|
Bar = GetUsbBar (HcToken);
|
|
DbgBar = Bar + (HcToken & B_TOKEN_DEBUG_CAP_INDEX);
|
|
if (DebugBar) *DebugBar = DbgBar;
|
|
//
|
|
// Set upstream non-posted request size to 1 if it is add-on PCIe XHCI card on Intel BayTrail chipset
|
|
//
|
|
if (((HcToken & B_TOKEN_XHCI_PCI_BRIDGE) >> N_TOKEN_XHCI_PCI_BRIDGE) != 0) {
|
|
//
|
|
// Set upstream non-posted request size in PCIe root bridge Channel Configuration(0xd0) bit 15 to 1
|
|
//
|
|
PciAddress = EFI_PCI_ADDRESS(0x00, ((HcToken & B_TOKEN_XHCI_PCI_DEV) >> N_TOKEN_XHCI_PCI_DEV), 0, 0);
|
|
Data = 0;
|
|
PciRead (EfiWidthUint16, PciAddress, &Data);
|
|
if (Data == 0x8086) {
|
|
PciRead (EfiWidthUint32, PciAddress + 0xd0, &Data);
|
|
if ((Data & 0x00008000) == 0) {
|
|
Data |= 0x00008000;
|
|
PciWrite (EfiWidthUint32, PciAddress + 0xd0, &Data);
|
|
}
|
|
}
|
|
}
|
|
//
|
|
// First pass for XHCI debug capability initial
|
|
//
|
|
while (RuntimeState) {
|
|
//
|
|
// HCRST detection during runtime for XHC debug capability recovery
|
|
//
|
|
Data = *(UINT32*)(UINTN)(Bar + (*(UINT32*)(UINTN)Bar & 0xff));
|
|
if (Data & 0x02) {
|
|
do {
|
|
Data = *(UINT32*)(UINTN)(Bar + (*(UINT32*)(UINTN)Bar & 0xff));
|
|
MicroSecondDelay (1000);
|
|
} while ((Data & 0x02) != 0);
|
|
RuntimeState = FALSE;
|
|
break;
|
|
}
|
|
//
|
|
// Debug capability changed detection
|
|
//
|
|
ReadXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCCTRL, &Data);
|
|
if (!(Data & B_DCCTRL_DCE)) {
|
|
RuntimeState = FALSE;
|
|
break;
|
|
}
|
|
|
|
//
|
|
// Intel port routing changed detection
|
|
//
|
|
if (HcToken & B_TOKEN_PORT_ROUTING) {
|
|
PciRead (EfiWidthUint32, PciAddress + 0xd0, &Data);
|
|
if (Data == 0) {
|
|
RuntimeState = FALSE;
|
|
break;
|
|
}
|
|
PciRead (EfiWidthUint32, PciAddress + 0xd8, &Data);
|
|
if (Data == 0) {
|
|
RuntimeState = FALSE;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
if (!RuntimeState) {
|
|
//
|
|
// Set XHC/EHC routing for Intel XHCI to make sure the signal routed to XHC
|
|
//
|
|
if (HcToken & B_TOKEN_PORT_ROUTING) {
|
|
Data = 0xffffffff;
|
|
PciWrite (EfiWidthUint32, PciAddress + 0xd0, &Data);
|
|
PciWrite (EfiWidthUint32, PciAddress + 0xd8, &Data);
|
|
MicroSecondDelay (100000);
|
|
}
|
|
Data = 0;
|
|
PciRead (EfiWidthUint16, PciAddress, &Data);
|
|
if (Data == 0x8086) {
|
|
|
|
//
|
|
// Host Controller Capability - 8070 h
|
|
// Xhci Capability Vendor Defined (ID: C0 h)
|
|
//
|
|
// Program xHCIBAR + 0x80B8 [5:0] - SSPE_REG: according to the number of enabled SuperSpeed port.
|
|
// The lower four bits represent the first four USB SuperSpeed ports
|
|
// and the upper two bits represent the two SSIC ports.
|
|
// [3:0]:Port 0 - Port 3
|
|
// [5:4]:SSIC Port 0 - Port 1
|
|
//
|
|
if ((*(UINT32*)(UINTN)(Bar + 0x8070) & 0xffff) == 0xffc0) {
|
|
*(UINT32*)(UINTN)(Bar + 0x80b8) |= 0x0000000f;
|
|
}
|
|
|
|
//
|
|
// SSIC Policy and Implementation Specific Registers - 0x8800
|
|
// PORT1_SSIC_CONFIG_REG2 - 880C h
|
|
// PORT2_SSIC_CONFIG_REG2 - 883c h
|
|
// Set PROG_DONE bit,
|
|
// xHCIBAR + 0x880C [30] = 1b and xHCIBAR + 0x883C [30] = 1b.
|
|
//
|
|
//
|
|
if ((*(UINT32*)(UINTN)(Bar + 0x8800) & 0xffff) == 0x40c4) {
|
|
*(UINT32*)(UINTN)(Bar + 0x880c) |= 0x40000000;
|
|
*(UINT32*)(UINTN)(Bar + 0x883c) |= 0x40000000;
|
|
}
|
|
//
|
|
// Set 64 byte DMA boundary(bit 22~25) and Read Request Size control(bit 0~3) on Intel BayTrail chipset
|
|
//
|
|
Data = 0x83cfc68f;
|
|
PciWrite (EfiWidthUint32, PciAddress + 0x44, &Data);
|
|
}
|
|
//
|
|
// Issue a HCRESET before initialization
|
|
//
|
|
*(UINT32*)(UINTN)(Bar + (*(UINT32*)(UINTN)Bar & 0xff)) = 0x02;
|
|
do {
|
|
Data = *(UINT32*)(UINTN)(Bar + (*(UINT32*)(UINTN)Bar & 0xff));
|
|
MicroSecondDelay (1000);
|
|
} while ((Data & 0x02) != 0);
|
|
|
|
//
|
|
// Allocate memory for the debug context
|
|
//
|
|
if (DebugContextAddr == NULL || *DebugContextAddr == 0) {
|
|
Pointer = 0x100000000;
|
|
Status = gBS->AllocatePages (
|
|
AllocateMaxAddress,
|
|
EfiACPIMemoryNVS,
|
|
1,
|
|
(EFI_PHYSICAL_ADDRESS*)&Pointer
|
|
);
|
|
if (Status != EFI_SUCCESS) {
|
|
return EFI_OUT_OF_RESOURCES;
|
|
}
|
|
DebugContext = (DBG_CONTEXT*)(UINTN)Pointer;
|
|
if (DebugContextAddr != NULL) *DebugContextAddr = (UINT32)(UINTN)DebugContext;
|
|
} else {
|
|
DebugContext = (DBG_CONTEXT*)(UINTN)*DebugContextAddr;
|
|
}
|
|
//
|
|
// Set LMC enable after HCRESET
|
|
//
|
|
ZeroMem (DebugContext, sizeof (DBG_CONTEXT));
|
|
DebugContext->LmcCapID |= B_LMC_LME;
|
|
} else {
|
|
//
|
|
// Get the debug context back from DCERSTBA
|
|
//
|
|
ReadXhcDebugReg (DbgBar, EfiWidthUint64, XHCI_DCERSTBA, &Pointer);
|
|
DebugContext = (DBG_CONTEXT*)(UINTN)(Pointer - (UINTN)&((DBG_CONTEXT*)0)->EventRingSegmentTable);
|
|
|
|
//
|
|
// Inspect the DCPORTSC to reinitial the debug port if port status changed
|
|
//
|
|
Data = 0;
|
|
ReadXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCPORTSC, &Data);
|
|
if (Data & (B_DCPORTSC_CSC | B_DCPORTSC_PRC | B_DCPORTSC_PLC | B_DCPORTSC_CEC)) {
|
|
//
|
|
// Port status changed, we need to recheck the port connection status without context update
|
|
//
|
|
UpdateContext = FALSE;
|
|
//
|
|
// Enable the port if it under disable state
|
|
//
|
|
if ((Data & B_DCPORTSC_CCS) && ((Data & B_DCPORTSC_PLS) >> N_DCPORTSC_PLS) == 0x04) {
|
|
Data |= B_DCPORTSC_PED;
|
|
WriteXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCPORTSC, &Data);
|
|
MicroSecondDelay (100000);
|
|
}
|
|
} else {
|
|
return EFI_SUCCESS;
|
|
}
|
|
}
|
|
if (!RuntimeState) {
|
|
//
|
|
// Setup Debug Context
|
|
//
|
|
DebugContext->Signature = USB_XHCID_SIGNATURE;
|
|
DebugContext->ContextSize = sizeof (DBG_CONTEXT);
|
|
DebugContext->EventRingSegmentTable.RingSegmentSize = EVENT_RING_SIZE;
|
|
DebugContext->DebugInfoContext.Str0Len = mStr0[0];
|
|
DebugContext->DebugInfoContext.ManufacturerLen = mManufacturer[0];
|
|
DebugContext->DebugInfoContext.ProductLen = mProduct[0];
|
|
DebugContext->DebugInfoContext.SerialNumLen = mSerialNum[0];
|
|
DebugContext->EndpointOut.MaxPacketSize = 0x400;
|
|
DebugContext->EndpointOut.ErrorCount = 3;
|
|
DebugContext->EndpointOut.EPType = EP_TYPE_BULK_OUT;
|
|
DebugContext->EndpointOut.AvgTRBLength = 0x400;
|
|
DebugContext->EndpointOut.MaxESITPayload = 0x400;
|
|
DebugContext->BulkOutTRB.TRBType = TRB_TYPE_NORMAL;
|
|
DebugContext->BulkOutTRB.IOC = 1;
|
|
DebugContext->BulkOutLinkTRB.ToggleCycle = 1;
|
|
DebugContext->BulkOutLinkTRB.TRBType = TRB_TYPE_LINK;
|
|
DebugContext->EndpointIn.MaxPacketSize = 0x400;
|
|
DebugContext->EndpointIn.ErrorCount = 3;
|
|
DebugContext->EndpointIn.EPType = EP_TYPE_BULK_IN;
|
|
DebugContext->EndpointIn.AvgTRBLength = 0x400;
|
|
DebugContext->EndpointIn.MaxESITPayload = 0x400;
|
|
DebugContext->BulkInTRB.TRBType = TRB_TYPE_NORMAL;
|
|
DebugContext->BulkInTRB.IOC = 1;
|
|
DebugContext->BulkInTRB.ISP = 1;
|
|
DebugContext->BulkInLinkTRB.ToggleCycle = 1;
|
|
DebugContext->BulkInLinkTRB.TRBType = TRB_TYPE_LINK;
|
|
CopyMem (DebugContext->Str0, mStr0, 0x10);
|
|
CopyMem (DebugContext->ManufacturerStr, mManufacturer, 0x10);
|
|
CopyMem (DebugContext->ProductStr, mProduct, 0x30);
|
|
CopyMem (DebugContext->SerialNum, mSerialNum, 0x10);
|
|
//
|
|
// Setup Debug Capability Registers
|
|
//
|
|
Data = 1;
|
|
WriteXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCERSTSZ, &Data);
|
|
Data = INSYDE_USB3D_VID << N_DCDDI1_VID;
|
|
WriteXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCDDI1, &Data);
|
|
Data = (INSYDE_USB3D_REV << N_DCDDI2_REV) + INSYDE_USB3D_PID;
|
|
WriteXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCDDI2, &Data);
|
|
}
|
|
if (UpdateContext) {
|
|
//
|
|
// Setup internal data pointers
|
|
//
|
|
DebugContext->EventRingSegmentTable.RingSegmentBaseAddress = (UINT64)(UINTN)DebugContext->Event;
|
|
DebugContext->DebugInfoContext.Str0DescAddr = (UINT64)(UINTN)DebugContext->Str0;
|
|
DebugContext->DebugInfoContext.ManufacturerDescAddr = (UINT64)(UINTN)DebugContext->ManufacturerStr;
|
|
DebugContext->DebugInfoContext.ProductDescAddr = (UINT64)(UINTN)DebugContext->ProductStr;
|
|
DebugContext->DebugInfoContext.SerialNumDescAddr = (UINT64)(UINTN)DebugContext->SerialNum;
|
|
DebugContext->EndpointOut.TRDequeuePointer = (UINT64)(UINTN)&DebugContext->BulkOutTRB | 0x01;
|
|
DebugContext->EndpointIn.TRDequeuePointer = (UINT64)(UINTN)&DebugContext->BulkInTRB | 0x01;
|
|
DebugContext->BulkOutLinkTRB.RingSegmentPointer = (UINT64)(UINTN)&DebugContext->BulkOutTRB;
|
|
DebugContext->BulkInLinkTRB.RingSegmentPointer = (UINT64)(UINTN)&DebugContext->BulkInTRB;
|
|
//
|
|
// Setup Debug Capability pointer registers
|
|
//
|
|
Pointer = (UINT64)(UINTN)&DebugContext->EventRingSegmentTable;
|
|
WriteXhcDebugReg (DbgBar, EfiWidthUint64, XHCI_DCERSTBA, &Pointer);
|
|
Pointer = (UINT64)(UINTN)DebugContext->Event;
|
|
WriteXhcDebugReg (DbgBar, EfiWidthUint64, XHCI_DCERDP, &Pointer);
|
|
Pointer = (UINT64)(UINTN)&DebugContext->DebugInfoContext;
|
|
WriteXhcDebugReg (DbgBar, EfiWidthUint64, XHCI_DCCP, &Pointer);
|
|
}
|
|
//
|
|
// Debug Capability Enable
|
|
//
|
|
Data = B_DCCTRL_DCE | B_DCCTRL_DRC;
|
|
WriteXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCCTRL, &Data);
|
|
//
|
|
// Route the port signal from ordinary USB3 port to debug port
|
|
//
|
|
RouteDebugPort (Bar);
|
|
//
|
|
// Waiting for USB3 debug port linked
|
|
//
|
|
PostCode = 0xd0;
|
|
Index = 0;
|
|
Timeout = XhcDebugIoConfig.Config.BypassTimeout * 2;
|
|
while (TRUE) {
|
|
ReadXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCCTRL, &Data);
|
|
if (Data & B_DCCTRL_DCR) break;
|
|
MicroSecondDelay (1000);
|
|
if (!Index) {
|
|
IoWrite8((UINT16)XhcDebugIoConfig.Config.DebugPort, PostCode);
|
|
PostCode = ByteRotate(PostCode);
|
|
Index = 500;
|
|
if (XhcDebugIoConfig.Config.Bypass) {
|
|
if (!Timeout) return EFI_TIMEOUT;
|
|
Timeout --;
|
|
}
|
|
}
|
|
Index --;
|
|
}
|
|
//
|
|
// Sets debug port for 0xd1 to indicate Xhci debug port ready
|
|
//
|
|
IoWrite8((UINT16)XhcDebugIoConfig.Config.DebugPort, 0xd1);
|
|
//
|
|
// Stall 3 seconds to waiting for host/device communication completed
|
|
//
|
|
MicroSecondDelay (3000000);
|
|
|
|
//
|
|
// Clear status registers
|
|
//
|
|
ReadXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCPORTSC, &Data);
|
|
WriteXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCPORTSC, &Data);
|
|
UpdateEventDequeuePointer(DbgBar, DebugContext, 0);
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
|
|
/**
|
|
Calculate the TD size based on xHCI interface version
|
|
|
|
@param [in] RemainingSize Remaining Byte Size
|
|
|
|
@return TD size
|
|
|
|
**/
|
|
STATIC
|
|
UINT32
|
|
CalcTDSize (
|
|
IN UINTN RemainingSize
|
|
)
|
|
{
|
|
UINT32 TDSize = (UINT32)(RemainingSize + 0x400 - 1) / 0x400;
|
|
return (TDSize < 0x1f) ? TDSize : 0x1f;
|
|
}
|
|
|
|
/**
|
|
UsbIoWrite.
|
|
|
|
@param [in] BufferSize
|
|
@param [in] Buffer
|
|
|
|
@retval EFI_SUCCESS
|
|
|
|
**/
|
|
EFI_STATUS
|
|
DebugXhcWrite(
|
|
IN DEBUG_IO_PRIVATE_DATA *Private,
|
|
IN UINTN BufferSize,
|
|
IN VOID *Buffer
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
UINT32 DbgBar;
|
|
UINT32 Data;
|
|
UINT64 Pointer;
|
|
DBG_CONTEXT *DebugContext;
|
|
UINT32 CycleBit;
|
|
UINT64 Tsc;
|
|
|
|
if (DetectXhci(&Private->HcToken, &DbgBar, &Private->DebugContextAddr) != EFI_SUCCESS) return EFI_DEVICE_ERROR;
|
|
//
|
|
// Get the debug context back from DCERSTBA
|
|
//
|
|
ReadXhcDebugReg (DbgBar, EfiWidthUint64, XHCI_DCERSTBA, &Pointer);
|
|
DebugContext = (DBG_CONTEXT*)(UINTN)(Pointer - (UINTN)&((DBG_CONTEXT*)0)->EventRingSegmentTable);
|
|
CycleBit = DebugContext->BulkOutTRB.CycleBit ^ 1;
|
|
DebugContext->BulkOutTRB.DataBufferPointer = (UINT64)(UINTN)Buffer;
|
|
DebugContext->BulkOutTRB.TransferLength = (UINT32)(BufferSize);
|
|
DebugContext->BulkOutTRB.CycleBit = CycleBit;
|
|
DebugContext->BulkOutTRB.TDSize = CalcTDSize(BufferSize);
|
|
DebugContext->BulkOutLinkTRB.CycleBit = CycleBit ^ 1;
|
|
//
|
|
// Ring the door bell
|
|
//
|
|
Data = 0x00000000;
|
|
WriteXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCDB, &Data);
|
|
Status = EFI_SUCCESS;
|
|
Tsc = 0;
|
|
while (TRUE) {
|
|
ReadXhcDebugReg (DbgBar, EfiWidthUint32, XHCI_DCST, &Data);
|
|
if (Data & B_DCST_ER) {
|
|
if (UpdateEventDequeuePointer(DbgBar, DebugContext, (UINT64)(UINTN)&DebugContext->BulkOutTRB)) break;
|
|
}
|
|
}
|
|
|
|
return Status;
|
|
}
|
|
|
|
|
|
/**
|
|
Prints a string to the USB port
|
|
|
|
@param [in] OutputString Ascii string to print to serial port.
|
|
|
|
@retval None
|
|
|
|
**/
|
|
VOID
|
|
EFIAPI
|
|
XhcDebugPrint (
|
|
IN CHAR8 *OutputString
|
|
)
|
|
{
|
|
UINTN StringLength;
|
|
CHAR8 *StringPtr;
|
|
UINT32 PciIndexSave;
|
|
DBG_CONTEXT *DbgContext;
|
|
CHAR8 *TempBuffer;
|
|
UINTN BufferLen;
|
|
DEBUG_IO_PRIVATE_DATA *Private;
|
|
EFI_STATUS Status;
|
|
|
|
Private = mPrivate;
|
|
if (Private == NULL) {
|
|
Status = gBS->LocateProtocol (
|
|
&mXhcDebugHobGuid,
|
|
NULL,
|
|
&Private
|
|
);
|
|
if (EFI_ERROR (Status)) {
|
|
return ;
|
|
}
|
|
mPrivate = Private;
|
|
}
|
|
|
|
DbgContext = (DBG_CONTEXT *) (UINTN) Private->DebugContextAddr;
|
|
TempBuffer = DbgContext->StringBuffer;
|
|
BufferLen = sizeof (DbgContext->StringBuffer);
|
|
|
|
//
|
|
// Save PCI index
|
|
//
|
|
PciIndexSave = IoRead32(0xcf8);
|
|
|
|
StringLength = AsciiStrLen (OutputString);
|
|
for (StringPtr = OutputString; StringLength >= BufferLen; StringLength -= BufferLen, StringPtr += BufferLen) {
|
|
CopyMem (TempBuffer, StringPtr, BufferLen);
|
|
DebugXhcWrite (Private, BufferLen, TempBuffer);
|
|
}
|
|
|
|
if (StringLength > 0) {
|
|
CopyMem (TempBuffer, StringPtr, StringLength);
|
|
DebugXhcWrite (Private, StringLength, TempBuffer);
|
|
}
|
|
|
|
//
|
|
// Restore PCI index
|
|
//
|
|
IoWrite32(0xcf8, PciIndexSave);
|
|
}
|
|
|
|
EFI_STATUS
|
|
EFIAPI
|
|
XhcInitializeStatusCode (
|
|
VOID
|
|
)
|
|
{
|
|
DEBUG_IO_PRIVATE_DATA *Private;
|
|
UINT32 PciIndexSave;
|
|
EFI_STATUS Status;
|
|
EFI_HANDLE Handle;
|
|
|
|
Status = gBS->LocateProtocol (
|
|
&mXhcDebugHobGuid,
|
|
NULL,
|
|
&Private
|
|
);
|
|
if (!EFI_ERROR (Status)) {
|
|
mPrivate = Private;
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
mPrivate = H2OAcpiNvsAllocate (sizeof (DEBUG_IO_PRIVATE_DATA));
|
|
if (mPrivate == NULL) {
|
|
return EFI_OUT_OF_RESOURCES;
|
|
}
|
|
|
|
ZeroMem (mPrivate, sizeof (DEBUG_IO_PRIVATE_DATA));
|
|
Private = GetFirstGuidHob (&mXhcDebugHobGuid);
|
|
if (Private != NULL) {
|
|
CopyMem (mPrivate, Private, sizeof (DEBUG_IO_PRIVATE_DATA));
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
Private = mPrivate;
|
|
|
|
PciIndexSave = IoRead32(0xcf8);
|
|
Status = DetectXhci(&Private->HcToken, NULL, NULL);
|
|
if (EFI_ERROR (Status)) {
|
|
IoWrite32(0xcf8, PciIndexSave);
|
|
return Status;
|
|
}
|
|
|
|
Status = InitXhciDebugPort(Private->HcToken, NULL, &Private->DebugContextAddr, FALSE);
|
|
if (EFI_ERROR (Status) && Status != EFI_TIMEOUT) {
|
|
IoWrite32(0xcf8, PciIndexSave);
|
|
return Status;
|
|
}
|
|
IoWrite32(0xcf8, PciIndexSave);
|
|
|
|
Handle = NULL;
|
|
Status = gBS->InstallProtocolInterface (
|
|
&Handle,
|
|
&mXhcDebugHobGuid,
|
|
EFI_NATIVE_INTERFACE,
|
|
Private
|
|
);
|
|
|
|
return Status;
|
|
}
|
|
|