121 lines
4.0 KiB
C
121 lines
4.0 KiB
C
/** @file
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;******************************************************************************
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;* Copyright (c) 2019 - 2020, Insyde Software Corporation. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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#ifndef _PEI_PCI_RESOURCE_INIT_H
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#define _PEI_PCI_RESOURCE_INIT_H
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#include <PiPei.h>
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#include <Guid/H2OCp.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PcdLib.h>
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#include <Library/HobLib.h>
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#include <Library/TimerLib.h>
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#include <Library/H2OCpLib.h>
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#include <Library/DeviceInfo2Lib.h>
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#include <IndustryStandard/Pci.h>
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#include <Ppi/EndOfPeiPhase.h>
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#include <Protocol/DevicePath.h>
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#define IS_ACPI_DP(a) ((((EFI_DEVICE_PATH_PROTOCOL *)a)->Type == ACPI_DEVICE_PATH) && (((EFI_DEVICE_PATH_PROTOCOL *)a)->SubType == ACPI_DP))
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#define IS_PCI_DP(a) ((((EFI_DEVICE_PATH_PROTOCOL *)a)->Type == HARDWARE_DEVICE_PATH) && (((EFI_DEVICE_PATH_PROTOCOL *)a)->SubType == HW_PCI_DP))
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#define FIRST_DOWNSTREAM_NUM 0x08
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#define PCI_BRIDGE_BASE_ADDRESS_REGISTER_OFFSET 0x20
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#define PCI_BRIDGE_PREFETCHABLE_BASE_ADDRESS_REGISTER_OFFSET 0x24
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#define PCI_BRIDGE_PREFETCHABLE_BASE_LIMIT_REGISTER_OFFSET 0x26
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#define PCI_BRIDGE_PREFETCHABLE_UPPER32BIT_BASE_ADDRESS_REGISTER_OFFSET 0x28
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#define PCI_BRIDGE_PREFETCHABLE_UPPER32BIT_BASE_LIMIT_REGISTER_OFFSET 0x2C
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#define PCI_INFO_NODE_FROM_LINK(a) CR (a, PCI_INFO_NODE, Link, PCI_INFO_NODE_SIGNATURE)
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#define PCI_INFO_NODE_SIGNATURE SIGNATURE_32 ('P', 'D', 'I', 'L')
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typedef struct {
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UINT32 NodeUid; // ACPI UID
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UINT8 Bus;
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UINT8 Device;
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UINT8 Function;
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UINT32 PciBar[PCI_MAX_BAR];
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} PCI_RESOURCE_DATA;
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typedef struct _PCI_INFO_NODE PCI_INFO_NODE;
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typedef PCI_INFO_NODE *PCI_INFO_NODE_PTR;
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struct _PCI_INFO_NODE {
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UINT32 Signature;
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LIST_ENTRY Link;
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PCI_RESOURCE_DATA PciRes;
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PCI_INFO_NODE *Parent;
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//
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// P2P Bridge
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//
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BOOLEAN IsP2pBridge;
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UINT8 SecondaryBus;
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UINT8 SubordinateBus;
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UINT32 MemBase;
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UINT32 MemLimit;
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};
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typedef
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EFI_STATUS
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(* CONTROLLER_INIT_ROUTINE) (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN PCI_RESOURCE_DATA *PciRes
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);
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/**
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Program BAR register for PCI device.
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@param [in] Bus PCI Bus number
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@param [in] Device PCI Device number
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@param [in] Function PCI Function number
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@param [in] BarIndex Index of BAR
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@param [in] BaseAddress Bass address
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@param [out] MmioSize MMIO size
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@retval EFI_SUCCESS Operation completed successfully
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@retval Others Operation failed
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**/
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EFI_STATUS
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ProgramBar (
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IN PCI_RESOURCE_DATA *PciRes
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);
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/**
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Register notify ppi to reset the bridges.
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@param[in] PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation
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@param[in] NotifyDescriptor Address of the notification descriptor data structure
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@param[in] Ppi Address of the PPI that was installed
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@retval EFI_SUCCESS Operation completed successfully
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@retval Others Operation failed
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**/
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EFI_STATUS
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EFIAPI
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BridgeEndOfPeiPpiNotifyCallback (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
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IN VOID *Ppi
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);
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#endif
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