134 lines
4.1 KiB
Plaintext
134 lines
4.1 KiB
Plaintext
/** @file
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ACPI DSDT table
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2011 - 2019 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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Scope (\_SB.PC00){
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Device(PDRC)
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{
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//
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// PCI Device Resource Consumption
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//
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Name(_HID,EISAID("PNP0C02"))
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Name(_UID,1)
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Name(BUF0,ResourceTemplate()
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{
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//
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// MCH BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.48h
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//
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Memory32Fixed(ReadWrite,0,0x08000,MCHB)
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//
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// DMI BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.68h
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//
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Memory32Fixed(ReadWrite,0,0x01000,DMIB)
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//
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// EP BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.40h
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//
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Memory32Fixed(ReadWrite,0,0x01000,EGPB)
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//
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// PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h
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//
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Memory32Fixed(ReadWrite,0,0,PCIX)
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//
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// PCH TXT space (Private / Public / TPM / DbC TraceHub / other)
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// Check if the hard code meets the real configuration.
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// If not, dynamically update it like the _CRS method below.
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//
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Memory32Fixed(ReadWrite,0xFED20000,0x60000)
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//
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// VTD engine memory range. Check if the hard code meets the real configuration.
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// If not, dynamically update it like the _CRS method below.
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//
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Memory32Fixed(ReadOnly, 0xFED90000, 0x00004000)
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//
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// MISC ICH. Check if the hard code meets the real configuration.
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// If not, dynamically update it like the _CRS method below.
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//
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Memory32Fixed(ReadWrite,0xFED45000,0x4B000,TPMM)
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//
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// Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
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//
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Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
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//
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// Sx handler reserved MMIO
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//
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Memory32Fixed (ReadWrite, 0, 0, SXRE)
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//
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// Reserve HPET address decode range
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//
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Memory32Fixed (ReadWrite, 0, 0, HPET)
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})
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Method(_CRS,0,Serialized)
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{
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CreateDwordField(BUF0,^MCHB._BAS,MBR0)
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Store(\_SB.PC00.GMHB(), MBR0)
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CreateDwordField(BUF0,^DMIB._BAS,DBR0)
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Store(\_SB.PC00.GDMB(), DBR0)
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CreateDwordField(BUF0,^EGPB._BAS,EBR0)
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Store(\_SB.PC00.GEPB(), EBR0)
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CreateDwordField(BUF0,^PCIX._BAS,XBR0)
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Store(\_SB.PC00.GPCB(), XBR0)
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CreateDwordField(BUF0,^PCIX._LEN,XSZ0)
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Store(\_SB.PC00.GPCL(), XSZ0)
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// HPET device claims the resource in LpcDev.asl.
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If(LNOT(HPTE)){
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CreateDwordField(BUF0,^HPET._BAS,HBAS)
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CreateDwordField(BUF0,^HPET._LEN,HLEN)
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Store(HPTB, HBAS)
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Store(0x400, HLEN)
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}
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Return(BUF0)
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}
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} //end of PDRC
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} // end of SB
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