604 lines
17 KiB
Plaintext
604 lines
17 KiB
Plaintext
/** @file
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ACPI RTD3 SSDT table for ADL N RVP
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2021 - 2022 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include <Include/AcpiDebug.h>
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DefinitionBlock (
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"Rtd3.aml",
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"SSDT",
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2,
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"Rtd3",
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"Adl_DDR4",
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0x1000
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)
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{
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External(S0ID)
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//
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//WWAN Pins
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//
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External(WRTO)
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External(WBRS)
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External(PBRS)
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External(PRST)
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External(WPRP)
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External(WFCP)
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External(PFCP)
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External(WWKP)
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External(WWEN)
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External(TPDT)
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External(TPLT)
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//
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//Pcie Slot 1 Pins
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//
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External(PSPR)
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External(PPSP)
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External(PSPE)
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External(PPSR)
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External(PSWP)
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//
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// Pch ssd Pins
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//
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External(SSDP)
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External(SSDR)
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External(SDRP)
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External(SDPP)
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//
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// Touch panel Pins
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//
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External(GPDI)
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External(GPLI)
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External(GPLP)
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External(GPLR)
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External(PPDI)
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External(PPLI)
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External(PPLP)
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External(PPLR)
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External(TPLS)
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//
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//WLAN wake Pins
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//
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External(WLWK)
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//
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//sata
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//
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External(SATP)
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External(STPP)
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//
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//GbE
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//
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External(GBED)
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External(XDCE)
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Include ("Rtd3Common.asl")
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#define WWAN_PCIE_ROOT_PORT \_SB.PC00.RP10
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External(WWAN_PCIE_ROOT_PORT.PXSX, DeviceObj)
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External(WWAN_PCIE_ROOT_PORT.LASX)
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External(\_SB.PC00.RP09.PXSX,DeviceObj)
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External(\_SB.PC00.RP04.PXSX.WIST,MethodObj)
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External(\_SB.PC00.XHCI.RHUB.HS08, DeviceObj)
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External(\_SB.GBTR, MethodObj)
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External(\_SB.BTRK, MethodObj)
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External(\_SB.PC00.I2C0, DeviceObj) //I2C0 Controller
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External(\_SB.PC00.I2C0.TPD0, DeviceObj) // Touch pad
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External(\_SB.PC00.I2C0.TPD0._STA, MethodObj)
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External(\_SB.PC00.I2C0.TPL1, DeviceObj) // Touch panel 2
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External(\_SB.PC00.I2C0.TPL1._STA, MethodObj)
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External(\_SB.PC00.HDAS, DeviceObj)
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External(\_SB.PC00.HDAS.VDID)
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External(\_SB.PC00.SAT0.PRT0.PRES, MethodObj)
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External(\_SB.PC00.SAT0.PRT1.PRES, MethodObj)
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//Board configuration
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//PCIe P3 -M.2 KEY E WWAN7360 -SRC CLK-NA(REWORK)(USB-BASED)
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//PCIe P4 -M.2 KEY B WLAN Wifi-BT -SRC CLK-2
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//PCIe P7 -x4 PCIe DT Slot (1Pair -x1 cem slot -sd card/TSN AIC) -SRC CLK-3
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//PCIe P9:P12 -PCIe X4 ssd -SRC CLK-0(LAN REVERSAL)
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//PCIe P10 -M.2 KEY E WWAN7560 -SRC CLK-NA(REWORK)
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//PCIe P11 -Sata Direct(SATA P0) SRC CLK-4 -(REWORK)
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//PCIe P12 -Sata Direct(SATA P1) SRC CLK-4 -(REWORK)
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// PCIe root ports - START
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/// PCIE RTD3 - PCIe M.2 CONNECTOR WWAN
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///
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If (LAnd(LNotEqual(WWEN,0),LNotEqual(WRTO,0))) {
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Scope(WWAN_PCIE_ROOT_PORT) {
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Name(BRST, Package() {0, 0})
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Store(WBRS, Index(BRST, 0))
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Store(PBRS, Index(BRST, 1))
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Name(RSTG, Package() {0, 0})
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Store(PRST, Index(RSTG, 0))
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Store(WPRP, Index(RSTG, 1))
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Name(PWRG, Package() {0, 0})
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Store(WFCP, Index(PWRG, 0))
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Store(PFCP, Index(PWRG, 1))
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Name(WAKG, 0)
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Store(WWKP, WAKG)
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Name(SCLK, 1)
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Include("Rtd3PcieWwan.asl")
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}
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}
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///
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/// PCIE RTD3 - PCIE SLOT 1 - X1 CONNECTOR
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///
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Scope(\_SB.PC00.RP07) {
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Name(RSTG, Package() {0, 0})
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Store(PSPR, Index(RSTG, 0))
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Store(PPSR, Index(RSTG, 1))
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Name(PWRG, Package() {0, 0})
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Store(PSPE, Index(PWRG, 0))
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Store(PPSP, Index(PWRG, 1))
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Name(WAKG, 0)
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Name(SCLK, 3)
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Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
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store(PSWP,WAKP)
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Include("PcieRpGenericPcieDeviceRtd3.asl")
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}
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///
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/// PCIe RP09 RTD3 - PCH M.2 SSD RTD3
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///
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//
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// Since WWAN and pch ssd shares same root port .
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// Added wwanrtd3 check on top before exposing pch ssd root port.
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//
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If (LEqual(WWEN,0)) {
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Scope(\_SB.PC00.RP09) {
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Name(RSTG, Package() {0, 0})
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Store(SSDR, Index(RSTG, 0))
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Store(SDRP, Index(RSTG, 1))
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Name(PWRG, Package() {0, 0})
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Store(SSDP, Index(PWRG, 0))
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Store(SDPP, Index(PWRG, 1))
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Name(WAKG, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
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Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
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Name(SCLK, 0)
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Include("PcieRpGenericPcieDeviceRtd3.asl")
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Scope(\_SB.PC00.RP09.PXSX) {
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Include("PcieRpSsdStorageRtd3Hook.asl")
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}
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}
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}
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// PCIe root ports - END
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//
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// SATA - START
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//
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Scope(\_SB.PC00.SAT0) {
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Scope(PRT0) {
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If (PRES ()) {
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Name(PWRG, Package() {0, 0})
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Store(SATP, Index(PWRG, 0))
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Store(STPP, Index(PWRG, 1))
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}
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}
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//
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// Same Power pin is used for pch ssd and sata.
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//
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Scope(PRT1) {
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If (PRES ()) {
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Name(PWRG, Package() {0, 0})
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Store(SSDP, Index(PWRG, 0))
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Store(SDPP, Index(PWRG, 1))
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}
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}
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Include("Rtd3Sata.asl")
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}
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//
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// SATA - END
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//
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//
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// USB - START
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//
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//
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// XDCI - start
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//
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If(LEqual(XDCE,1)) {
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Scope(\_SB)
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{
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//
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// Dummy power resource for USB D3 cold support
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//
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PowerResource(USBC, 0, 0)
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{
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Method(_STA) { Return (0xF) }
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Method(_ON) {}
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Method(_OFF) {}
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}
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}
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Scope(\_SB.PC00.XDCI)
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{
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OperationRegion (GENR, SystemMemory, Add(And(XDCB, 0xFFFFFFFFFFFFFF00), 0x10F81C), 0x4) //AON MMIO - 10F81C: APBFC_U3PMU_CFG5
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Field (GENR, WordAcc, NoLock, Preserve)
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{
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, 2,
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CPME, 1, //bit2 core_pme_en
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U3EN, 1, //bit3 u3_pme_en
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U2EN, 1 //bit4 u2_pme_en
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}
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Method (_PS3, 0, NotSerialized)
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{
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Store (One, CPME)
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Store (One, U2EN)
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Store (One, U3EN)
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\_SB.CSD3(MODPHY_SPD_GATING_XDCI)
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}
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Method (_PS0, 0, NotSerialized)
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{
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Store (Zero, CPME)
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Store (Zero, U2EN)
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Store (Zero, U3EN)
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If(LEqual(DVID,0xFFFF)) {
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Return()
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}
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\_SB.CSD0(MODPHY_SPD_GATING_XDCI)
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}
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Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
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{
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Return (Zero)
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}
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Method (_PR3, 0, NotSerialized) // _PR3: Power Resources for D3hot
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{
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Return (Package (0x01)
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{
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USBC // return dummy package
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})
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}
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} // Scope(\_SB.PC00.XDCI)
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} // XDCE
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//
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// XDCI - end
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//
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//
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// USB - END
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//
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If (LNotEqual(GBES,0)) {
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Scope(\_SB.PC00.GLAN)
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{
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Method (_PS3, 0, NotSerialized)
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{
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\_SB.CSD3(MODPHY_SPD_GATING_GBE)
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}
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Method (_PS0, 0, NotSerialized)
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{
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If(LNot(GBED)){ // If GBE_FDIS_PMC == 0
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\_SB.CSD0(MODPHY_SPD_GATING_GBE)
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}
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}
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} // Scope(\_SB.PC00.GLAN)
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}
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//
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// Human Interface Devices Start
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//
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//
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//
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// PCH I2C0 - TouchPad Power control
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//
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Scope(\_SB.PC00.I2C0){
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Method(PS0X,0,Serialized)
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{
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}
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/// PS3X Method, called by PS3 method in PchSerialIo.asl
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Method(PS3X,0,Serialized)
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{
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}
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/// \ref i2c0_pr_pxtc
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///@defgroup i2c0_scope I2C1 Scope
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If (LNotEqual(TPDT,0)) {
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PowerResource(PXTC, 0, 0){
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Method(_STA){
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Return(PSTA(0))
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}
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Method(_ON){
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PON(0)
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}
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Method(_OFF){
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POFF(0)
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}
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} // End PXTC
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}
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/// \ref i2c0_pr_ptpl
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///@defgroup i2c0_scope
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If (LNotEqual(TPLT,0)) {
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PowerResource(PTPL, 0, 0){
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Method(_STA){
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Return(PSTA(1))
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}
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Method(_ON){
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PON(1)
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}
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Method(_OFF){
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POFF(1)
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}
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}
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}
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/// Variable:
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Name(ONTM, 0) ///ONTM: 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON
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Method(PSTA, 1, Serialized){
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If (Arg0 == 0) {
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Return(0x01)
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}
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If (Arg0 == 1) {
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If(LEqual(\_SB.GGOV(GPLP), 1)) {
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Return(0x01)
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} Else {
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Return(0x00)
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}
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}
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Return(0x00)
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}
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// Timing of Power and Reset for I2C Touch Panel
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// _____________________________________________________________________________________________________
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// | minimum required time | Reset de-assert from Power On (ms) | Power Off from Reset assert (ms)|
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// |_______________________|_______________________________________|_____________________________________|
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// | current setting | 2 | 3 |
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// |_______________________|_______________________________________|_____________________________________|
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// * no maximum time limitation.
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Method(PON, 1, Serialized) /// _ON Method \n Turn on
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{
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If (Arg0 == 0) {
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// enable int line
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\_SB.SGRA(GPDI, PPDI)
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}
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ElseIf (Arg0 == 1) {
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// drive pwr high
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\_SB.SGOV(GPLP, PPLP)
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Sleep(2) // time for Reset de-assert from Power On
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// De-Assert GPIO RST
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\_SB.SGOV(GPLR, PPLR)
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// update ONTM
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Store(Timer(), ONTM)
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// enable int line
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\_SB.SGRA(GPLI, PPLI)
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}
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}
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Method(POFF, 1, Serialized) /// _OFF method \n Turn off
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{
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If (Arg0 == 0) {
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// disable int line
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Xor(PPDI, 1, Local0)
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\_SB.SGRA(GPDI, Local0)
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}
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ElseIf (Arg0 == 1) {
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// disable int line
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Xor(PPLI, 1, Local0)
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\_SB.SGRA(GPLI, Local0)
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// Assert GPIO RST
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Xor(PPLR, 1, Local0)
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\_SB.SGOV(GPLR, Local0)
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Sleep(3) // time for Power Off from Reset assert
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// drive pwr low
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Xor(PPLP, 1, Local0)
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\_SB.SGOV(GPLP, Local0)
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// update ONTM
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Store(Zero , ONTM) ///- Clear ONTM
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}
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}
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If (LNotEqual(TPDT,0)) {
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Scope(TPD0){
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Name (TD_P, Package(){\_SB.PC00.I2C0.PXTC}) // TD_P - Touch Device Power Package
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Alias(IC0D, TD_D) // TD_D - Touch Device power on delay
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Alias(\_SB.PC00.I2C0.ONTM, TD_C) // TD_C - Touch Device I2C controller power on timestamp
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Include("Rtd3I2cTouchDev.asl")
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Method(_PS0) { PS0X() }
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Method(_PS3) { PS3X() }
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}// End Of Scope(TPD0)
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}
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If (LNotEqual(TPLT,0)) {
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Scope(TPL1){
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Name (TD_P, Package(){\_SB.PC00.I2C0.PTPL}) // TD_P - Touch Device Power Package
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Alias(IC1D, TD_D) // TD_D - Touch Device power on delay
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Alias(\_SB.PC00.I2C0.ONTM, TD_C) // TD_C - Touch Device I2C controller power on timestamp
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Include("Rtd3I2cTouchDev.asl")
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Method(_PS0) { PS0X() }
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Method(_PS3) { PS3X() }
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}// End Of Scope(TPL1)
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}
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} // Scope(\_SB.PC00.I2C0)
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//
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//Power Resource for Audio Codec
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Scope(\_SB.PC00)
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{
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PowerResource(PAUD, 0, 0) {
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/// Namespace variable used:
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Name(PSTA, One) /// PSTA: Physical Power Status of Codec 0 - OFF; 1-ON
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Name(ONTM, Zero) /// ONTM: 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON
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Name(_STA, One) /// _STA: PowerResource Logical Status 0 - OFF; 1-ON
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///@defgroup pr_paud Power Resource for onboard Audio CODEC
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Method(_ON, 0){ /// _ON method \n
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Store(One, _STA) ///- Set Logocal power state
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PUAM() ///- Call PUAM() to tansition Physical state to match current logical state
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///@addtogroup pr_paud
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} // End _ON
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Method(_OFF, 0){ /// _OFF method \n
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Store(Zero, _STA) ///- Set the current power state
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PUAM() ///- Call PUAM() to tansition Physical state to match current logical state
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///@addtogroup pr_paud
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} // End _OFF
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/// PUAM - Power Resource User Absent Mode for onboard Audio CODEC
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/// Arguments:
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///
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/// Uses:
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/// _STA - Variable updated by Power Resource _ON/_OFF methods \n
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/// \\UAMS - Variable updated by GUAM method to show User absent present \n
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/// ONTM - Local variable to store ON time during Speculative ON \n
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/// ______________________________
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// | Inputs | Outputs |
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// ______________________________
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// | _STA | \UAMS | GPIO | ONTM |
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// ______________________________
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// | 1 | 0 | ON | !0 |
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// | 1 | !0 | ON | !0 |
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// | 0 | 0 | ON | !0 |
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// | 0 | !0 | OFF | 0 |
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// ______________________________
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/**
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<table>
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<tr> <th colspan="2"> Inputs <th colspan="2"> Output
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<tr> <th>_STA <th> \\UAMS <th> GPIO <th>ONTM
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<tr> <td>1 <td>0 <td>ON <td>!0
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<tr> <td>1 <td>!0<td>ON <td>!0
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<tr> <td>0 <td>0 <td>ON <td>!0
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<tr> <td>0 <td>!0<td>OFF<td> 0
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</table>
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**/
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///@addtogroup pr_paud_puam
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Method(PUAM, 0, Serialized)
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{
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// power rail = NOT there for ICL U
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// Note:- Audio Power enable need not be implemented by default and need rework if we need power control.
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If (LAnd(LEqual(^_STA, Zero), LNotEqual(\UAMS, Zero))) { ///New state = OFF Check if (_STA ==0 && \UAMS != 0) \n
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} Else { /// New state = ON (_STA=1) or (_STA=0 and \UAMS=0)
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|
/// Turn power on \n
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|
If(LNotEqual(^PSTA, One)) { ///- Skip below if Power Resource is already in ON
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|
Store(One, ^PSTA) ///- >> Set PSTA to 1
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|
Store(Timer(), ^ONTM) ///- >> Start the timer for this PR
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}
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}
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///@defgroup pr_paud_puam Power Resource User Absent Mode for onboard Audio CODEC
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} //PUAM
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} //PAUD
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} //Scope(\_SB.PC00)
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|
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//
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|
// Check HDAS (HD-Audio) controller present
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|
//
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|
If(LNotEqual(\_SB.PC00.HDAS.VDID, 0xFFFFFFFF)) {
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|
Scope(\_SB.PC00.HDAS) {
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|
Method(PS0X,0,Serialized) /// Platform D0 Method for HD-A Controller
|
|
{
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|
If(LEqual(\_SB.PC00.PAUD.ONTM, Zero)){ ///- Check if ONTM=0
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|
Return()
|
|
}
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|
|
|
///
|
|
///- Make sure "D0 delay" (AUDD) delay is elapsed before returning _PS0
|
|
///- Local0: Elapse time since the _ON method
|
|
///- VRRD: VR Rampup Delay
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|
///- AUDD: Time required for device to be ready after power on
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|
///- Local1 = AUDD + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay
|
|
///- So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method
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|
///
|
|
Divide(Subtract(Timer(), \_SB.PC00.PAUD.ONTM), 10000, , Local0) ///- Store Elapsed time in ms, ignore remainder
|
|
Add(AUDD, VRRD, Local1) ///- Incorporate VR Rampup Delay
|
|
If(LLess(Local0, Local1)) { ///- Do not sleep if already past the delay requirement audio
|
|
///- Delay for device init
|
|
Sleep(Subtract(Local1, Local0)) ///- Sleep (AUDD + VRRD - time elapsed)
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|
}
|
|
}
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|
|
|
///Associate _PR0 with \ref pr_paud
|
|
Name(_PR0, Package(){\_SB.PC00.PAUD})
|
|
///@defgroup hdef_scope Intel High Definition Audio Scope
|
|
}
|
|
}// If(LNotEqual(\_SB.PC00.HDAS.VDID, 0xFFFFFFFF))
|
|
//GPE Event handling - Start
|
|
Scope(\_GPE) {
|
|
//
|
|
// Alternate _L6F(), to handle 2-tier RTD3 GPE events here
|
|
//
|
|
Method(AL6F) {
|
|
// WLAN wake event
|
|
If (\_SB.ISME(WLWK))
|
|
{
|
|
\_SB.SHPO(WLWK, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
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|
Notify(\_SB.PC00.RP04, 0x02) // device wake
|
|
\_SB.CAGS(WLWK) // WIFI_WAKE_N
|
|
}
|
|
|
|
//Wwan wake event
|
|
If (\_SB.ISME(WWKP))
|
|
{
|
|
\_SB.SHPO(WWKP, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
|
|
Notify(WWAN_PCIE_ROOT_PORT, 0x02) // device wake
|
|
\_SB.CAGS(WWKP) // WWAN_WAKE_N
|
|
}
|
|
|
|
//Pcie x1 DT slot wake event
|
|
If (\_SB.ISME(PSWP))
|
|
{
|
|
\_SB.SHPO(PSWP, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
|
|
Notify(\_SB.PC00.RP07, 0x02) // device wake
|
|
\_SB.CAGS(PSWP)
|
|
}
|
|
}
|
|
} //Scope(\_GPE)
|
|
//GPE Event handling - End
|
|
} // End SSDT
|