517 lines
16 KiB
Plaintext
517 lines
16 KiB
Plaintext
/** @file
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ACPI RTD3 SSDT table for ADL P DG128 AEP
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include <Include/AcpiDebug.h>
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DefinitionBlock (
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"Rtd3.aml",
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"SSDT",
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2,
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"Rtd3",
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"AdlP_128",
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0x1000
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)
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{
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External(S0ID)
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//
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//WWAN Pins
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//
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External(WRTO)
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External(WBRS)
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External(PBRS)
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External(PRST)
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External(WPRP)
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External(WFCP)
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External(PFCP)
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External(WWKP)
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// Touch Pad
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External(TPDT)
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//
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// CPU ssd1 Pins
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//
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External(SDR1)
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External(SDP1)
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External(SD2R)
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External(SDR2)
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External(SD2P)
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//
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// CPU ssd2 Pins
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//
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External(SD5R)
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External(SDR5)
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External(SD5P)
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External(SDP5)
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//
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// DG Pins
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//
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External(DG2P)
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External(DGP2)
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External(DGR2)
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External(DG2R)
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External(P1WP)
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External(XDCE)
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//
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// Touch Pins
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//
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External(GPDI)
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External(PPDI)
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//
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//Vmd Pins
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//
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External(VMDE)
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Include ("Rtd3Common.asl")
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#define WWAN_PCIE_ROOT_PORT \_SB.PC00.RP06
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External(WWAN_PCIE_ROOT_PORT.PXSX, DeviceObj)
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External(WWAN_PCIE_ROOT_PORT.LASX)
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External(\_SB.PC00.PEG0.PEGP,DeviceObj)
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External(\_SB.PC00.PEG1.PEGP,DeviceObj)
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External(\_SB.PC00.PEG2.PEGP,DeviceObj)
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External(\_SB.PC00.XHCI.RHUB.HS10, DeviceObj)
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External(\_SB.GBTR, MethodObj)
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External(\_SB.BTRK, MethodObj)
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External(\_SB.PC00.UA02.BTH0, DeviceObj)
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External(\_SB.PC00.I2C0, DeviceObj) //I2C0 Controller
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External(\_SB.PC00.I2C0.TPD0, DeviceObj) // Touch pad
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External(\_SB.PC00.I2C0.TPD0._STA, MethodObj)
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External(\_SB.PC00.I2C1, DeviceObj) //I2C1 Controller
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External(\_SB.PC00.I2C1.TPL1._STA, MethodObj)
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External(\_SB.PC00.HDAS, DeviceObj)
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External(\_SB.PC00.HDAS.VDID)
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//Board configuration
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//PCIe P6 -M.2 KEY B WWAN -SRC CLK-5
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//PCIe4/PEG0 P0:P3- X4 SSD1 -SRC CLK-4
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//PCIe5/PEG1 P0:P7- X8 DG/DG2 -SRC CLK-3
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//PCIe4/PEG2 P4:P7- X4 SSD2 -SRC CLK-6
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// PCIe root ports - START
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///
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/// PCIE RTD3 - PCIe M.2 CONNECTOR WWAN
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///
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If (LNotEqual(WRTO,0)) {
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Scope(WWAN_PCIE_ROOT_PORT) {
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Name(BRST, Package() {0, 0})
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Store(WBRS, Index(BRST, 0))
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Store(PBRS, Index(BRST, 1))
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Name(RSTG, Package() {0, 0})
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Store(PRST, Index(RSTG, 0))
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Store(WPRP, Index(RSTG, 1))
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Name(PWRG, Package() {0, 0})
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Store(WFCP, Index(PWRG, 0))
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Store(PFCP, Index(PWRG, 1))
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Name(WAKG, 0)
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Store(WWKP, WAKG)
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Name(SCLK, 5)
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Include("Rtd3PcieWwan.asl")
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}
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}
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///
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/// CPU M.2 SSD RTD3
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///
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// SD2P, 32, // [M2Ssd3PowerEnableGpio ] PCIe x4 M.2 SSD Power Enable Gpio pin
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// SDP1, 8, // [M2Ssd3PowerEnableGpioPolarity ] PCIe x4 M.2 SSD Power Enable Gpio pin polarity
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// SD2R, 32, // [M2Ssd3RstGpio ] PCIe x4 M.2 SSD Reset Gpio pin
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// SDR1, 8, // [M2Ssd3RstGpioPolarity ] PCIe x4 M.2 SSD Reset Gpio pin polarity
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Name(RSTG, Package() {0, 0})
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Name(PWRG, Package() {0, 0})
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Store(SD2R, Index(RSTG, 0))
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Store(SDR1, Index(RSTG, 1))
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Store(SD2P, Index(PWRG, 0))
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Store(SDP1, Index(PWRG, 1))
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Name(WAKG, 0)
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Store(0, WAKG)
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Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
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Name(SCLK, 8)
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Include("PcieRpGenericPcieDeviceRtd3.asl")
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Scope(\_SB.PC00.PEG0.PEGP) {
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Include("PcieRpSsdStorageRtd3Hook.asl")
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}
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}
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///
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/// CPU M.2 SSD RTD3
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///
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// SD5P, 32, // [M2Ssd3PowerEnableGpio ] PCIe x4 M.2 SSD Power Enable Gpio pin
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// SDP5, 8, // [M2Ssd3PowerEnableGpioPolarity ] PCIe x4 M.2 SSD Power Enable Gpio pin polarity
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// SD5R, 32, // [M2Ssd3RstGpio ] PCIe x4 M.2 SSD Reset Gpio pin
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// SDR5, 8, // [M2Ssd3RstGpioPolarity ] PCIe x4 M.2 SSD Reset Gpio pin polarity
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Scope(\_SB.PC00.PEG2) {
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Name(RSTG, Package() {0, 0})
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Name(PWRG, Package() {0, 0})
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Store(SD5R, Index(RSTG, 0))
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Store(SDR5, Index(RSTG, 1))
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Store(SD5P, Index(PWRG, 0))
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Store(SDP5, Index(PWRG, 1))
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Name(WAKG, 0)
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Store(0, WAKG)
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Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
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Name(SCLK, 6)
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Include("PcieRpGenericPcieDeviceRtd3.asl")
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Scope(\_SB.PC00.PEG2.PEGP) {
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Include("PcieRpSsdStorageRtd3Hook.asl")
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}
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}
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///
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/// PEG PCIE RTD3 - PEG PCIE SLOT 3 - X8 CONNECTOR
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///
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// DG2P, 32, // [M2DG2PowerEnableGpio ] PCIe x5 M.2 Discrete Graphics Power Enable Gpio Pin
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// DGP2, 8, // [M2DG2PowerEnableGpioPolarity ] PCIe x5 M.2 Discrete Graphics Power Enable Gpio Pin polarity
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// DG2R, 32, // [M2DG2RstGpio ] PCIe x5 M.2 Discrete Graphics Reset Gpio Pin
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// DGR2, 8, // [M2DG2RstGpioPolarity ] PCIe x5 M.2 Discrete Graphics Reset Gpio Pin Polarity
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Scope(\_SB.PC00.PEG1) {
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Name(RSTG, Package() {0, 0})
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Name(PWRG, Package() {0, 0})
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Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
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Name(SCLK, 3)
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Store(DG2R, Index(RSTG, 0))
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Store(DGR2, Index(RSTG, 1))
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Store(DG2P, Index(PWRG, 0))
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Store(DGP2, Index(PWRG, 1))
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Name(WAKG, 0)
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Store(P1WP, WAKG)
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// Note: IPC1 Command Timeout need to increase for dGPU only.
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Name (TMCS, 3000) // IPC Command Timeout Increase to 3 Secs.
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If(LNotEqual (DGBA, 0)) {
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Include("PcieRpDiscreteGraphicsDeviceRtd3Hook.asl")
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}
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Scope(\_SB.PC00.PEG1.PEGP) {
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Include("PcieRpSsdStorageRtd3Hook.asl")
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}
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Include("PcieRpGenericPcieDeviceRtd3.asl")
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}
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// PCIe root ports - END
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//
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// VMD - START
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//
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#if (FixedPcdGetBool (PcdVmdEnable) == 1)
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Include ("Rtd3Vmd.asl")
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#endif
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//
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// VMD - END
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//
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//
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// USB - START
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//
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//
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// XDCI - start
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//
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If(LEqual(XDCE,1)) {
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Scope(\_SB)
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{
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//
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// Dummy power resource for USB D3 cold support
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//
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PowerResource(USBC, 0, 0)
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{
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Method(_STA) { Return (0xF) }
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Method(_ON) {}
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Method(_OFF) {}
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}
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}
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Scope(\_SB.PC00.XDCI)
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{
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OperationRegion (GENR, SystemMemory, Add(And(XDCB, 0xFFFFFFFFFFFFFF00), 0x10F81C), 0x4) //AON MMIO - 10F81C: APBFC_U3PMU_CFG5
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Field (GENR, WordAcc, NoLock, Preserve)
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{
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, 2,
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CPME, 1, //bit2 core_pme_en
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U3EN, 1, //bit3 u3_pme_en
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U2EN, 1 //bit4 u2_pme_en
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}
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Method (_PS3, 0, NotSerialized)
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{
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Store (One, CPME)
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Store (One, U2EN)
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Store (One, U3EN)
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\_SB.CSD3(MODPHY_SPD_GATING_XDCI)
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}
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Method (_PS0, 0, NotSerialized)
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{
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Store (Zero, CPME)
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Store (Zero, U2EN)
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Store (Zero, U3EN)
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If(LEqual(DVID,0xFFFF)) {
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Return()
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}
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\_SB.CSD0(MODPHY_SPD_GATING_XDCI)
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}
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Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
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{
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Return (Zero)
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}
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Method (_PR3, 0, NotSerialized) // _PR3: Power Resources for D3hot
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{
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Return (Package (0x01)
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{
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USBC // return dummy package
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})
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}
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} // Scope(\_SB.PC00.XDCI)
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} // XDCE
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//
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// XDCI - end
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//
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//
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// USB - END
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//
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//
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// Human Interface Devices Start
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//
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//
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//
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// PCH I2C0 - TouchPad Power control
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//
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Scope(\_SB.PC00.I2C0){
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Method(PS0X,0,Serialized)
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{
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}
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/// PS3X Method, called by PS3 method in PchSerialIo.asl
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Method(PS3X,0,Serialized)
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{
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}
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/// \ref i2c0_pr_pxtc
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///@defgroup i2c0_scope I2C1 Scope
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If (LNotEqual(TPDT,0)) {
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PowerResource(PXTC, 0, 0){
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Method(_STA){
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Return(PSTA(0))
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}
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Method(_ON){
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PON(0)
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}
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Method(_OFF){
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POFF(0)
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}
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} // End PXTC
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}
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/// Variable:
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Name(ONTM, 0) ///ONTM: 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON
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Method(PSTA, 1, Serialized){
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If (Arg0 == 0) {
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Return(0x01)
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}
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Return(0x00)
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}
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Method(PON, 1, Serialized) /// _ON Method \n Turn on
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{
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If (Arg0 == 0) {
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// enable int line
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\_SB.SGRA(GPDI, PPDI)
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}
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}
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Method(POFF, 1, Serialized) /// _OFF method \n Turn off
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{
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If (Arg0 == 0) {
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// disable int line
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Xor(PPDI, 1, Local0)
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\_SB.SGRA(GPDI, Local0)
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}
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}
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If (LNotEqual(TPDT,0)) {
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Scope(TPD0){
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Name (TD_P, Package(){\_SB.PC00.I2C0.PXTC}) // TD_P - Touch Device Power Package
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Alias(IC0D, TD_D) // TD_D - Touch Device power on delay
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Alias(\_SB.PC00.I2C0.ONTM, TD_C) // TD_C - Touch Device I2C controller power on timestamp
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Include("Rtd3I2cTouchDev.asl")
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Method(_PS0) { PS0X() }
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Method(_PS3) { PS3X() }
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}// End Of Scope(TPD0)
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}
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}// Scope(\_SB.PC00.I2C0)
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//
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//Power Resource for Audio Codec
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Scope(\_SB.PC00)
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{
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PowerResource(PAUD, 0, 0) {
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/// Namespace variable used:
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Name(PSTA, One) /// PSTA: Physical Power Status of Codec 0 - OFF; 1-ON
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Name(ONTM, Zero) /// ONTM: 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON
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Name(_STA, One) /// _STA: PowerResource Logical Status 0 - OFF; 1-ON
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///@defgroup pr_paud Power Resource for onboard Audio CODEC
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Method(_ON, 0){ /// _ON method \n
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Store(One, _STA) ///- Set Logocal power state
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PUAM() ///- Call PUAM() to tansition Physical state to match current logical state
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///@addtogroup pr_paud
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} // End _ON
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Method(_OFF, 0){ /// _OFF method \n
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Store(Zero, _STA) ///- Set the current power state
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PUAM() ///- Call PUAM() to tansition Physical state to match current logical state
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///@addtogroup pr_paud
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} // End _OFF
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/// PUAM - Power Resource User Absent Mode for onboard Audio CODEC
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/// Arguments:
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///
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/// Uses:
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/// _STA - Variable updated by Power Resource _ON/_OFF methods \n
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/// \\UAMS - Variable updated by GUAM method to show User absent present \n
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/// ONTM - Local variable to store ON time during Speculative ON \n
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/// ______________________________
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// | Inputs | Outputs |
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// ______________________________
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// | _STA | \UAMS | GPIO | ONTM |
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// ______________________________
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// | 1 | 0 | ON | !0 |
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// | 1 | !0 | ON | !0 |
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// | 0 | 0 | ON | !0 |
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// | 0 | !0 | OFF | 0 |
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// ______________________________
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/**
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<table>
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<tr> <th colspan="2"> Inputs <th colspan="2"> Output
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<tr> <th>_STA <th> \\UAMS <th> GPIO <th>ONTM
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<tr> <td>1 <td>0 <td>ON <td>!0
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<tr> <td>1 <td>!0<td>ON <td>!0
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<tr> <td>0 <td>0 <td>ON <td>!0
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<tr> <td>0 <td>!0<td>OFF<td> 0
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</table>
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**/
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///@addtogroup pr_paud_puam
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Method(PUAM, 0, Serialized)
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{
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// power rail = NOT there for ICL U
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// Note:- Audio Power enable need not be implemented by default and need rework if we need power control.
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If (LAnd(LEqual(^_STA, Zero), LNotEqual(\UAMS, Zero))) { ///New state = OFF Check if (_STA ==0 && \UAMS != 0) \n
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} Else { /// New state = ON (_STA=1) or (_STA=0 and \UAMS=0)
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/// Turn power on \n
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If(LNotEqual(^PSTA, One)) { ///- Skip below if Power Resource is already in ON
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Store(One, ^PSTA) ///- >> Set PSTA to 1
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Store(Timer(), ^ONTM) ///- >> Start the timer for this PR
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}
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}
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///@defgroup pr_paud_puam Power Resource User Absent Mode for onboard Audio CODEC
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} //PUAM
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} //PAUD
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} //Scope(\_SB.PC00)
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//
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// Check HDAS (HD-Audio) controller present
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//
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If(LNotEqual(\_SB.PC00.HDAS.VDID, 0xFFFFFFFF)) {
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Scope(\_SB.PC00.HDAS) {
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Method(PS0X,0,Serialized) /// Platform D0 Method for HD-A Controller
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{
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If(LEqual(\_SB.PC00.PAUD.ONTM, Zero)){ ///- Check if ONTM=0
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Return()
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}
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///
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///- Make sure "D0 delay" (AUDD) delay is elapsed before returning _PS0
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///- Local0: Elapse time since the _ON method
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///- VRRD: VR Rampup Delay
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///- AUDD: Time required for device to be ready after power on
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///- Local1 = AUDD + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay
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///- So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method
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///
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Divide(Subtract(Timer(), \_SB.PC00.PAUD.ONTM), 10000, , Local0) ///- Store Elapsed time in ms, ignore remainder
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Add(AUDD, VRRD, Local1) ///- Incorporate VR Rampup Delay
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If(LLess(Local0, Local1)) { ///- Do not sleep if already past the delay requirement audio
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///- Delay for device init
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Sleep(Subtract(Local1, Local0)) ///- Sleep (AUDD + VRRD - time elapsed)
|
|
}
|
|
}
|
|
|
|
///Associate _PR0 with \ref pr_paud
|
|
Name(_PR0, Package(){\_SB.PC00.PAUD})
|
|
///@defgroup hdef_scope Intel High Definition Audio Scope
|
|
}
|
|
}// If(LNotEqual(\_SB.PC00.HDAS.VDID, 0xFFFFFFFF))
|
|
//GPE Event handling - Start
|
|
Scope(\_GPE) {
|
|
Method(_L14) {
|
|
If (\_SB.ISME(P1WP))
|
|
{
|
|
\_SB.SHPO(P1WP, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
|
|
If (CondRefOf(\_SB.PC00.PEG1)) {
|
|
If(LNotEqual(\_SB.PC00.PEG1.VDID,0xFFFFFFFF)) { // If Device present in X8 slot
|
|
Notify(\_SB.PC00.PEG1, 0x02) // device wake
|
|
}
|
|
}
|
|
\_SB.CAGS(P1WP)
|
|
}
|
|
}
|
|
//
|
|
// Alternate _L6F(), to handle 2-tier RTD3 GPE events here
|
|
//
|
|
Method(AL6F) {
|
|
//Wwan wake event
|
|
If (\_SB.ISME(WWKP))
|
|
{
|
|
\_SB.SHPO(WWKP, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
|
|
Notify(WWAN_PCIE_ROOT_PORT, 0x02) // device wake
|
|
\_SB.CAGS(WWKP) // WWAN_WAKE_N
|
|
}
|
|
}
|
|
} //Scope(\_GPE)
|
|
//GPE Event handling - End
|
|
} // End SSDT
|