1044 lines
34 KiB
Plaintext
1044 lines
34 KiB
Plaintext
/** @file
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;******************************************************************************
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;* Copyright 2021 Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corp.
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;*
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;******************************************************************************
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*/
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/** @file
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ACPI RTD3 SSDT table for ADL S SODIMM RVP (TBT version)
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include <Include/AcpiDebug.h>
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DefinitionBlock (
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"Rtd3.aml",
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"SSDT",
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2,
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"Rtd3",
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"AdlS8Tbt",
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0x1000
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)
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{
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External(RTD3, IntObj)
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External(S0ID)
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External(OSYS)
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External(HGMD)
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External(\ECON, IntObj)
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External(GBED)
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External(SDS9)
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Include ("Rtd3Common.asl")
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External(\_SB.PC00.HDAS, DeviceObj)
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External(\_SB.PC00.HDAS.VDID)
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External(PEPC)
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External(WRTO)
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External(PRST)
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External(WPRP)
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External(WFCP)
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External(PFCP)
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External(WBRS)
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External(PBRS)
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External(GPDI)
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External(GPLI)
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External(GPLP)
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External(GPLR)
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External(GPI1)
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External(TPP1)
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External(TPR1)
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External(PPDI)
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External(PPLI)
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External(PPLP)
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External(PPLR)
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External(PPI1)
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External(PPP1)
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External(PPR1)
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External(PSPE)
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External(PPSP)
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External(PSPR)
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External(PPSR)
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External(PSWP)
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External(RPNB)
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External(PSW2)
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External(RPN2)
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External(PSP2)
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External(PS2P)
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External(PSR2)
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External(PSP3)
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External(PS3P)
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External(PSR3)
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External(SR3P)
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External(PSW3)
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External(RPN3)
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External(SR2P)
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External(WLWK)
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External(SATP)
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External(STPP)
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External(SSDP)
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External(SDPP)
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External(SSDR)
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External(SDRP)
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External(SD2P)
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External(SDP1)
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External(SD2R)
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External(SDR1)
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External(SD3P)
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External(SDP3)
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External(SD3R)
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External(SDR3)
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External(SD4P)
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External(SDP4)
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External(SD4R)
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External(SDR4)
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External(TPLS)
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External(P1PE)
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External(P1PP)
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External(P1RE)
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External(P1RP)
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External(P1WP)
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External(PRP1)
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External(P2PE)
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External(P2PP)
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External(P2RE)
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External(P2RP)
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External(P2WP)
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External(PRP2)
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External(VMDE)
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External(FVWP)
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External(FVRE)
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External(FVRP)
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External(FVPE)
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External(FVPP)
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External(FVSP)
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External(OMP1)
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External(OM1P)
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External(OMR1)
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External(MR1P)
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External(OMW1)
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External(RPO1)
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External(\DTWA, IntObj)
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External(\_SB.PEPD, DeviceObj)
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External(\_SB.GHPO, MethodObj)
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External(\_SB.SHPO, MethodObj)
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External(\_SB.PC00.LPCB.H_EC.PVOL)
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External(\_SB.PC00.XHCI.RHUB.HS14, DeviceObj)
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External(\_SB.PC00.RP08.PXSX.WIST, MethodObj)
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External(\_SB.GBTR, MethodObj)
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External(\_SB.BTRK, MethodObj)
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External(\_SB.PC00.UA00.BTH0, DeviceObj)
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External(\_SB.PC00.PEG0.PEGP, DeviceObj)
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External(\_SB.PC00.RP13.PXSX, DeviceObj)
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External(\_SB.PC00.RP01.PXSX, DeviceObj)
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External(\_SB.PC00.RP25.PXSX, DeviceObj)
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External(\_SB.PC00.I2C1, DeviceObj)
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External(\_SB.PC00.I2C1.TPL1, DeviceObj)
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External(\_SB.PC00.I2C1.TPL1._STA, MethodObj)
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External(SPPR) // PchNvs SataPortPresence
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External(\PSOC, MethodObj) // PS_ON control method
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External(\PSOS, MethodObj) // PS_ON status method
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External(\RPSC, MethodObj) // PS_ON D3cold mask method
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External(\_SB.PC00.XHCI.PDPG, MethodObj) // ECless PD power managment support
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External(PPOE, IntObj) // PD PD_ON Enabled
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//
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// Platform power distribution description.
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// Keep the power resources in the "\" scope
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// to allow Windows to disable them if they are not
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// referenced by any devices. Windows will not turn off
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// unused power resources located in device scope.
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//
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Scope(\) {
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Include ("PsonVeto.asl")
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//
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// Note: SATA PRT0~3 on ADL-S is conencted to M.2 slot
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// and will be powered up from the auxilary power supply during
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// PS_ON so it does not depend on ATX power resource.
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//
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PowerResource(SPR4, 0, 0) {
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Method(_STA) {Return(\STMS(4))}
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Method(_ON) {\STMC(4, 1)}
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Method(_OFF) {\STMC(4, 0)}
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}
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PowerResource(SPR5, 0, 0) {
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Method(_STA) {Return(\STMS(5))}
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Method(_ON) {\STMC(5, 1)}
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Method(_OFF) {\STMC(5, 0)}
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}
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PowerResource(SPR6, 0, 0) {
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Method(_STA) {Return(\STMS(6))}
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Method(_ON) {\STMC(6, 1)}
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Method(_OFF) {\STMC(6, 0)}
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}
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PowerResource(SPR7, 0, 0) {
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Method(_STA) {Return(\STMS(7))}
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Method(_ON) {\STMC(7, 1)}
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Method(_OFF) {\STMC(7, 0)}
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}
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} // End of Scope(\)
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// PCIe root ports - START
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///
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/// PCIE RTD3 - PCIE SLOT 1 - X4 CONNECTOR
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///
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//PSPE, 32, // [PcieSlot1PowerEnableGpio ] Pcie Slot 1 Power Enable Gpio pin
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//PPSP, 8, // [PcieSlot1PowerEnableGpioPolarity ] Pcie Slot 1 Power Enable Gpio pin polarity
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//PSPR, 32, // [PcieSlot1RstGpio ] Pcie Slot 1 Rest Gpio pin
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//PPSR, 8, // [PcieSlot1RstGpioPolarity ] Pcie Slot 1 Rest Gpio pin polarity
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//PSWP, 32, // [PcieSlot1WakeGpio ] Pcie Slot Wake Gpio pin
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Scope(\_SB.PC00.RP21) {
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Name(RSTG, Package() {0, 0})
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Store(PSPR, Index(RSTG, 0))
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Store(PPSR, Index(RSTG, 1))
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Name(PWRG, Package() {0, 0})
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Store(PSPE, Index(PWRG, 0))
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Store(PPSP, Index(PWRG, 1))
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Name(WAKG, 0)
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Store(PSWP, WAKG)
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Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
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Name(SCLK, 2)
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//
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// CEM slot power limit
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// note: even though PCIe CEM form factor
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// defines maximum auxilary power as 1238mW
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// our PCIe CEM slots can safely handle 3300mW.
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//
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Name(PSPL, 3300)
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//
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// Block core power removal.
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// Arg0 - 0: Allow for core power removal, 1: block core power removal
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//
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Method(BCPR, 1, Serialized) {\PCPA(0, Arg0)}
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Method(CEMP, 1, Serialized) {\RPSC(0, Arg0)}
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Include("PcieAuxDSD.asl")
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Include("PcieAuxPowerBudgeting.asl")
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//[-start-211125-IB05660187-add]//
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#undef DGPU_BRIDGE_SCOPE
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#undef DGPU_DEVICE
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#define DGPU_BRIDGE_SCOPE \_SB.PC00.RP21
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#define DGPU_DEVICE PXSX
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//[-end-211125-IB05660187-add]//
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Include("PcieRpGenericPcieDeviceRtd3.asl")
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}
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///
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/// PCIE RTD3 - PCIE SLOT 2 - X4 CONNECTOR
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///
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//PSP2, 32, // [PcieSlot2PowerEnableGpio ] Pcie Slot 2 Power Enable Gpio pin
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//PS2P, 8, // [PcieSlot2PowerEnableGpioPolarity ] Pcie Slot 2 Power Enable Gpio pin polarity
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//PSR2, 32, // [PcieSlot2RstGpio ] Pcie Slot 2 Rest Gpio pin
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//SR2P, 8, // [PcieSlot2RstGpioPolarity ] Pcie Slot 2 Rest Gpio pin polarity
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//PSW2, 32, // [PcieSlot2WakeGpio ] Pcie Slot 2 Wake Gpio pin
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Scope(\_SB.PC00.RP09) {
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Name(RSTG, Package() {0, 0})
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Store(PSR2, Index(RSTG, 0))
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Store(SR2P, Index(RSTG, 1))
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Name(PWRG, Package() {0, 0})
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Store(PSP2, Index(PWRG, 0))
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Store(PS2P, Index(PWRG, 1))
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Name(WAKG, 0)
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Store(PSW2, WAKG)
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Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
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Name(SCLK, 14)
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//
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// CEM slot power limit
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// note: even though PCIe CEM form factor
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// defines maximum auxilary power as 1238mW
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// our PCIe CEM slots can safely handle 3300mW.
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//
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Name(PSPL, 3300)
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//
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// Block core power removal.
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// Arg0 - 0: Allow for core power removal, 1: block core power removal
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//
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Method(BCPR, 1, Serialized) {\PCPA(1, Arg0)}
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Method(CEMP, 1, Serialized) {\RPSC(1, Arg0)}
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Include("PcieAuxDSD.asl")
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Include("PcieAuxPowerBudgeting.asl")
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//[-start-211125-IB05660187-add]//
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#undef DGPU_BRIDGE_SCOPE
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#undef DGPU_DEVICE
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#define DGPU_BRIDGE_SCOPE \_SB.PC00.RP09
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#define DGPU_DEVICE PXSX
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//[-end-211125-IB05660187-add]//
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Include("PcieRpGenericPcieDeviceRtd3.asl")
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}
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///
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/// PCIE RTD3 - PCIE SLOT 3 - X2 CONNECTOR
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///
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//PSP3, 32, // [PcieSlot3PowerEnableGpio ] Pcie Slot 3 Power Enable Gpio pin
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//PS3P, 8, // [PcieSlot3PowerEnableGpioPolarity ] Pcie Slot 3 Power Enable Gpio pin polarity
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//PSR3, 32, // [PcieSlot3RstGpio ] Pcie Slot 3 Rest Gpio pin
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//SR3P, 8, // [PcieSlot3RstGpioPolarity ] Pcie Slot 3 Rest Gpio pin polarity
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//PSW3, 32, // [PcieSlot3WakeGpio ] Pcie Slot Wake Gpio pin
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Scope(\_SB.PC00.RP05) {
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Name(RSTG, Package() {0, 0})
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Store(PSR3, Index(RSTG, 0))
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Store(SR3P, Index(RSTG, 1))
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Name(PWRG, Package() {0, 0})
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Store(PSP3, Index(PWRG, 0))
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Store(PS3P, Index(PWRG, 1))
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Name(WAKG, 0)
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Store(PSW3, WAKG)
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Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
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Name(SCLK, 15)
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//
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// CEM slot power limit
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// note: even though PCIe CEM form factor
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// defines maximum auxilary power as 1238mW
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// our PCIe CEM slots can safely handle 3300mW.
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//
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Name(PSPL, 3300)
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//
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// Block core power removal.
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// Arg0 - 0: Allow for core power removal, 1: block core power removal
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//
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Method(BCPR, 1, Serialized) {\PCPA(2, Arg0)}
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Method(CEMP, 1, Serialized) {\RPSC(2, Arg0)}
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Include("PcieAuxDSD.asl")
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Include("PcieAuxPowerBudgeting.asl")
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//[-start-211125-IB05660187-add]//
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#undef DGPU_BRIDGE_SCOPE
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#undef DGPU_DEVICE
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#define DGPU_BRIDGE_SCOPE \_SB.PC00.RP05
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#define DGPU_DEVICE PXSX
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//[-end-211125-IB05660187-add]//
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Include("PcieRpGenericPcieDeviceRtd3.asl")
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}
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///
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/// PCH M.2 SSD RTD3
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///
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//SSDP, 32, // [PchM2SsdPowerEnableGpio ] Pch M.2 SSD Power Enable Gpio pin
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//SDPP, 8, // [PchM2SsdPowerEnableGpioPolarity ] Pch M.2 SSD Power Enable Gpio pin polarity
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//SSDR, 32, // [PchM2SsdRstGpio ] Pch M.2 SSD Reset Gpio pin
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//SDRP, 8, // [PchM2SsdRstGpioPolarity ] Pch M.2 SSD Reset Gpio pin polarity
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Scope(\_SB.PC00.RP13) {
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Name(RSTG, Package() {0, 0})
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Store(SSDR, Index(RSTG, 0))
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Store(SDRP, Index(RSTG, 1))
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Name(PWRG, Package() {0, 0})
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Store(SSDP, Index(PWRG, 0))
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Store(SDPP, Index(PWRG, 1))
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Name(WAKG, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
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Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
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Name(SCLK, 12)
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//[-start-211125-IB05660187-add]//
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#undef DGPU_BRIDGE_SCOPE
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#undef DGPU_DEVICE
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#define DGPU_BRIDGE_SCOPE \_SB.PC00.RP13
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#define DGPU_DEVICE PXSX
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//[-end-211125-IB05660187-add]//
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Include("PcieRpGenericPcieDeviceRtd3.asl")
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Scope(\_SB.PC00.RP13.PXSX) {
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Include("PcieRpSsdStorageRtd3Hook.asl")
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}
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}
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#ifndef PCH_ADPP
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///
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/// Onboard MR 1
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///
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//OMP1, 32, // [OnBoardMr1PowerEnableGpio ] Onboard MR 1 Power Enable Gpio pin
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//OM1P, 8, // [OnBoardMr1PowerEnableGpioPolarity ] Onboard MR 1 Power Enable Gpio pin polarity
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//OMR1, 32, // [OnBoardMr1RstGpio ] Onboard MR 1 Rest Gpio pin
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//MR1P, 8, // [OnBoardMr1RstGpioPolarity ] Onboard MR 1 Rest Gpio pin polarity
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//OMW1, 32, // [OnBoardMr1WakeGpio ] Onboard MR 1 Wake Gpio pin
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Scope(\_SB.PC00.RP25) {
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Name(RSTG, Package() {0, 0})
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Store(OMR1, Index(RSTG, 0))
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Store(MR1P, Index(RSTG, 1))
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Name(PWRG, Package() {0, 0})
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Store(OMP1, Index(PWRG, 0))
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Store(OM1P, Index(PWRG, 1))
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Name(WAKG, 0)
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Store(OMW1, WAKG)
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Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
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Name(SCLK, 13)
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Name(TUID, 0) // TBT RP Number 0 for RP25
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Include("Rtd3PcieTbt.asl")
|
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//
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// The PRx resource list is dependend on how many groups added.
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//
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Method (_PR0) {
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If( LAnd (LNotEqual (PPOE, 0), CondRefOf (\_SB.PC00.XHCI.PDPG))) {
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Return (Package(){\_SB.PC00.XHCI.PDPG, \_SB.PC00.RP25.PXP})
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} else {
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Return (Package(){\_SB.PC00.RP25.PXP})
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}
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}
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Method (_PR3) {
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If( LAnd (LNotEqual (PPOE, 0), CondRefOf (\_SB.PC00.XHCI.PDPG))) {
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Return (Package(){\_SB.PC00.XHCI.PDPG, \_SB.PC00.RP25.PXP})
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} else {
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Return (Package(){\_SB.PC00.RP25.PXP})
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}
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}
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Method (SXWK, 0, Serialized) { // Enable DTbt PCIE RP Wake capability from Sx
|
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// enable WAKE
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If (LAnd (CondRefOf (WAKG), CondRefOf (\DTWA))) {
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If(LAnd (LNotEqual (WAKG, 0), \DTWA)) {
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\_SB.CAGS (WAKG) // Clear Pending Wake GPIO Interrupt.
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\_SB.SHPO (WAKG, 0) // Enable Wake GPIO.
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}
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}
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}
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}
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#endif
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///
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/// PCH M.2 SSD3 RTD3
|
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///
|
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//SD4P, 32, // [PchM2Ssd3PowerEnableGpio ] Pch M.2 SSD3 Power Enable Gpio pin
|
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//SDP4, 8, // [PchM2Ssd3PowerEnableGpioPolarity ] Pch M.2 SSD3 Power Enable Gpio pin polarity
|
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//SD4R, 32, // [PchM2Ssd3RstGpio ] Pch M.2 SSD3 Reset Gpio pin
|
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//SDR4, 8, // [PchM2Ssd3RstGpioPolarity ] Pch M.2 SSD3 Reset Gpio pin polarity
|
|
Scope(\_SB.PC00.RP01) {
|
|
Name(RSTG, Package() {0, 0})
|
|
Store(SD4R, Index(RSTG, 0))
|
|
Store(SDR4, Index(RSTG, 1))
|
|
Name(PWRG, Package() {0, 0})
|
|
Store(SD4P, Index(PWRG, 0))
|
|
Store(SDP4, Index(PWRG, 1))
|
|
Name(WAKG, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
|
|
Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
|
|
Name(SCLK, 10)
|
|
//[-start-211125-IB05660187-add]//
|
|
#undef DGPU_BRIDGE_SCOPE
|
|
#undef DGPU_DEVICE
|
|
#define DGPU_BRIDGE_SCOPE \_SB.PC00.RP01
|
|
#define DGPU_DEVICE PXSX
|
|
//[-end-211125-IB05660187-add]//
|
|
Include("PcieRpGenericPcieDeviceRtd3.asl")
|
|
Scope(\_SB.PC00.RP01.PXSX) {
|
|
Include("PcieRpSsdStorageRtd3Hook.asl")
|
|
}
|
|
}
|
|
|
|
///
|
|
/// CPU M.2 SSD RTD3
|
|
///
|
|
//SD2P, 32, // [M2Ssd2PowerEnableGpio ] PCIe x4 M.2 SSD Power Enable Gpio pin
|
|
//SDP1, 8, // [M2Ssd2PowerEnableGpioPolarity ] PCIe x4 M.2 SSD Power Enable Gpio pin polarity
|
|
//SD2R, 32, // [M2Ssd2RstGpio ] PCIe x4 M.2 SSD Reset Gpio pin
|
|
//SDR1, 8, // [M2Ssd2RstGpioPolarity ] PCIe x4 M.2 SSD Reset Gpio pin polarity
|
|
Scope(\_SB.PC00.PEG0) {
|
|
Name(RSTG, Package() {0, 0})
|
|
Store(SD2R, Index(RSTG, 0))
|
|
Store(SDR1, Index(RSTG, 1))
|
|
Name(PWRG, Package() {0, 0})
|
|
Store(SD2P, Index(PWRG, 0))
|
|
Store(SDP1, Index(PWRG, 1))
|
|
Name(WAKG, 0)
|
|
Name(WAKP, 0) // must be defined due to compiler bug, will be removed when fixed https://bugs.acpica.org/show_bug.cgi?id=1432
|
|
Name(SCLK, 11)
|
|
//[-start-211125-IB05660187-add]//
|
|
#undef DGPU_BRIDGE_SCOPE
|
|
#undef DGPU_DEVICE
|
|
#define DGPU_BRIDGE_SCOPE \_SB.PC00.PEG0
|
|
#define DGPU_DEVICE PEGP
|
|
//[-end-211125-IB05660187-add]//
|
|
Include("PcieRpGenericPcieDeviceRtd3.asl")
|
|
Scope(\_SB.PC00.PEG0.PEGP) {
|
|
Include("PcieRpSsdStorageRtd3Hook.asl")
|
|
}
|
|
}
|
|
///
|
|
/// CPU PEG1
|
|
///
|
|
//P1PE, 32, // [PegSlot1PwrEnableGpioNo ] PEG slot 1 Power Enable Gpio pin
|
|
//P1PP, 8, // [PegSlot1PwrEnableGpioPolarity ] PEG slot 1 Power Enable Gpio pin polarity
|
|
//P1RE, 32, // [PegSlot1RstGpioNo ] PEG slot 1 Reset Gpio pin
|
|
//P1RP, 8, // [PegSlot1RstGpioPolarity ] PEG slot 1 Reset Gpio pin polarity
|
|
//P1WP, 32, // [PegSlot1WakeGpioPin ] PEG slot 1 Wake Gpio pin
|
|
//PRP1, 8, // [PegSlot1RootPort ] PEG slot 1 Root Port
|
|
Scope(\_SB.PC00.PEG1) {
|
|
Name(RSTG, Package() {0, 0})
|
|
Store(P1RE, Index(RSTG, 0))
|
|
Store(P1RP, Index(RSTG, 1))
|
|
Name(PWRG, Package() {0, 0})
|
|
Store(P1PE, Index(PWRG, 0))
|
|
Store(P1PP, Index(PWRG, 1))
|
|
Name(WAKG, 0)
|
|
Store(P1WP, WAKG)
|
|
Name(WAKP, 0)
|
|
Name(SCLK, 0)
|
|
//
|
|
// CEM slot power limit
|
|
// note: even though PCIe CEM form factor
|
|
// defines maximum auxilary power as 1238mW
|
|
// our PCIe CEM slots can safely handle 3300mW.
|
|
//
|
|
Name(PSPL, 3300)
|
|
//
|
|
// Block core power removal.
|
|
// Arg0 - 0: Allow for core power removal, 1: block core power removal
|
|
//
|
|
Method(BCPR, 1, Serialized) {\PCPA(3, Arg0)}
|
|
Method(CEMP, 1, Serialized) {\RPSC(3, Arg0)}
|
|
Include("PcieAuxPowerBudgeting.asl")
|
|
//[-start-211125-IB05660187-add]//
|
|
#undef DGPU_BRIDGE_SCOPE
|
|
#undef DGPU_DEVICE
|
|
#define DGPU_BRIDGE_SCOPE \_SB.PC00.PEG1
|
|
#define DGPU_DEVICE PEGP
|
|
//[-end-211125-IB05660187-add]//
|
|
Include("PcieRpGenericPcieDeviceRtd3.asl")
|
|
}
|
|
///
|
|
/// CPU PEG2
|
|
///
|
|
//P2PE, 32, // [PegSlot2PwrEnableGpioNo ] PEG slot 2 Power Enable Gpio pin
|
|
//P2PP, 8, // [PegSlot2PwrEnableGpioPolarity ] PEG slot 2 Power Enable Gpio pin polarity
|
|
//P2RE, 32, // [PegSlot2RstGpioNo ] PEG slot 2 Reset Gpio pin
|
|
//P2RP, 8, // [PegSlot2RstGpioPolarity ] PEG slot 2 Reset Gpio pin polarity
|
|
//P2WP, 32, // [PegSlot2WakeGpioPin ] PEG slot 2 Wake Gpio pin
|
|
//PRP2, 8, // [PegSlot2RootPort ] PEG slot 2 Root Port
|
|
|
|
//Check P2PP value here to distinquish if it's BoardIdAdlSAdpSDdr5UDimm1DCrb or
|
|
//BoardIdAdlSAdpSDdr4UDimm2DCrb. Ddr5 board has No PEG2 Slot, so donot need handle RTD3
|
|
if (LNotEqual(P2PP,0)) {
|
|
Scope(\_SB.PC00.PEG2) {
|
|
Name(RSTG, Package() {0, 0})
|
|
Store(P2RE, Index(RSTG, 0))
|
|
Store(P2RP, Index(RSTG, 1))
|
|
Name(PWRG, Package() {0, 0})
|
|
Store(P2PE, Index(PWRG, 0))
|
|
Store(P2PP, Index(PWRG, 1))
|
|
Name(WAKG, 0)
|
|
Store(P1WP, WAKG)
|
|
Name(WAKP, 0)
|
|
Name(SCLK, 1)
|
|
//
|
|
// CEM slot power limit
|
|
// note: even though PCIe CEM form factor
|
|
// defines maximum auxilary power as 1238mW
|
|
// our PCIe CEM slots can safely handle 3300mW.
|
|
//
|
|
Name(PSPL, 3300)
|
|
//
|
|
// Block core power removal.
|
|
// Arg0 - 0: Allow for core power removal, 1: block core power removal
|
|
//
|
|
Method(BCPR, 1, Serialized) {\PCPA(4, Arg0)}
|
|
Method(CEMP, 1, Serialized) {\RPSC(4, Arg0)}
|
|
Include("PcieAuxPowerBudgeting.asl")
|
|
//[-start-211125-IB05660187-add]//
|
|
#undef DGPU_BRIDGE_SCOPE
|
|
#undef DGPU_DEVICE
|
|
#define DGPU_BRIDGE_SCOPE \_SB.PC00.PEG2
|
|
#define DGPU_DEVICE PEGP
|
|
//[-end-211125-IB05660187-add]//
|
|
Include("PcieRpGenericPcieDeviceRtd3.asl")
|
|
}
|
|
}
|
|
|
|
///
|
|
/// 2.5Gbe LAN Foxville I225
|
|
///
|
|
|
|
//FVWP, 32, // [FoxLanWakeGpio ] Foxville I225 Wake Gpio pin
|
|
//FVRE, 32, // [FoxLanRstGpio ] Foxville I225 Reset Gpio pin
|
|
//FVRP, 8, // [FoxLanRstGpioPolarity ] Foxville I225 Reset Gpio pin polarity
|
|
//FVPE, 32, // [FoxLanDisableNGpio ] Foxville I225 Disable N Gpio pin
|
|
//FVPP, 8, // [FoxLanDisableNGpioPolarity] Foxville I225 Disable N Gpio pin polarity
|
|
//FVSP, 8, // [FoxLanSupport] Foxville I225 support configuration
|
|
If(LEqual(FVSP,1)) {
|
|
Scope(\_SB.PC00.RP07) {
|
|
Name(RSTG, Package() {0, 0})
|
|
Store(FVRE, Index(RSTG, 0))
|
|
Store(FVRP, Index(RSTG, 1))
|
|
Name(PWRG, Package() {0, 0})
|
|
Store(FVPE, Index(PWRG, 0))
|
|
Store(FVPP, Index(PWRG, 1))
|
|
Name(WAKG, 0)
|
|
Store(FVWP, WAKG)
|
|
Name(WAKP, 0)
|
|
Name(SCLK, 5)
|
|
//[-start-211125-IB05660187-add]//
|
|
#undef DGPU_BRIDGE_SCOPE
|
|
#undef DGPU_DEVICE
|
|
#define DGPU_BRIDGE_SCOPE \_SB.PC00.RP07
|
|
#define DGPU_DEVICE PXSX
|
|
//[-end-211125-IB05660187-add]//
|
|
Include("PcieRpGenericPcieDeviceRtd3.asl")
|
|
}
|
|
}
|
|
// PCIe root ports - END
|
|
|
|
//
|
|
// SATA - START
|
|
//
|
|
Scope(\_SB.PC00.SAT0) {
|
|
Scope(PRT4) {
|
|
Name(_S0W, 4)
|
|
Method(SPON) {
|
|
\STMC(4, 1)
|
|
}
|
|
Method(SPOF) {
|
|
\STMC(4, 0)
|
|
}
|
|
//
|
|
// Check with PRES method if SATA port is present
|
|
// and if OS will be able to enumerate it. We can't return
|
|
// PowerResources for devices that won't be enumerated since
|
|
// Windows won't turn off power resources for such devices.
|
|
//
|
|
External(PRES, MethodObj)
|
|
If (PRES()) {
|
|
Method(_PR0) {Return(Package() {SPR4})}
|
|
Method(_PR3) {Return(Package() {SPR4})}
|
|
}
|
|
}
|
|
|
|
Scope(PRT5) {
|
|
Name(_S0W, 4)
|
|
Method(SPON) {
|
|
\STMC(5, 1)
|
|
}
|
|
Method(SPOF) {
|
|
\STMC(5, 0)
|
|
}
|
|
External(PRES, MethodObj)
|
|
If (PRES()) {
|
|
Method(_PR0) {Return(Package() {SPR5})}
|
|
Method(_PR3) {Return(Package() {SPR5})}
|
|
}
|
|
}
|
|
|
|
Scope(PRT6) {
|
|
Name(_S0W, 4)
|
|
Method(SPON) {
|
|
\STMC(6, 1)
|
|
}
|
|
Method(SPOF) {
|
|
\STMC(6, 0)
|
|
}
|
|
External(PRES, MethodObj)
|
|
If (PRES()) {
|
|
Method(_PR0) {Return(Package() {SPR6})}
|
|
Method(_PR3) {Return(Package() {SPR6})}
|
|
}
|
|
}
|
|
|
|
Scope(PRT7) {
|
|
Name(_S0W, 4)
|
|
Method(SPON) {
|
|
\STMC(7, 1)
|
|
}
|
|
Method(SPOF) {
|
|
\STMC(7, 0)
|
|
}
|
|
External(PRES, MethodObj)
|
|
If (PRES()) {
|
|
Method(_PR0) {Return(Package() {SPR7})}
|
|
Method(_PR3) {Return(Package() {SPR7})}
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// SATA - END
|
|
//
|
|
//
|
|
|
|
//
|
|
// VMD - START
|
|
//
|
|
#if (FixedPcdGetBool (PcdVmdEnable) == 1)
|
|
Include ("Rtd3Vmd.asl")
|
|
#endif
|
|
//
|
|
// VMD - END
|
|
//
|
|
|
|
// USB - START
|
|
//
|
|
|
|
//
|
|
// Report BT power resource if CNVd BT is UART.
|
|
//
|
|
If (LEqual (SDS9, 2)) { // Only required for CNVd BT over UART selection
|
|
Scope (\_SB.PC00.UA00.BTH0) {
|
|
Method(_PS0, 0, Serialized)
|
|
{
|
|
\_SB.BTRK (0x01) // Turn on BT
|
|
}
|
|
Method(_PS3, 0, Serialized)
|
|
{
|
|
\_SB.BTRK (0x00) // Turn off BT
|
|
}
|
|
}
|
|
}
|
|
|
|
External(XDCE)
|
|
//
|
|
// XDCI - start
|
|
//
|
|
If(LEqual(XDCE,1)) {
|
|
Scope(\_SB)
|
|
{
|
|
//
|
|
// Dummy power resource for USB D3 cold support
|
|
//
|
|
PowerResource(USBC, 0, 0)
|
|
{
|
|
Method(_STA) { Return (0xF) }
|
|
Method(_ON) {}
|
|
Method(_OFF) {}
|
|
}
|
|
}
|
|
|
|
Scope(\_SB.PC00.XDCI)
|
|
{
|
|
OperationRegion (GENR, SystemMemory, Add(And(XDCB, 0xFFFFFFFFFFFFFF00), 0x10F81C), 0x4) //AON MMIO - 10F81C: APBFC_U3PMU_CFG5
|
|
Field (GENR, WordAcc, NoLock, Preserve)
|
|
{
|
|
, 2,
|
|
CPME, 1, //bit2 core_pme_en
|
|
U3EN, 1, //bit3 u3_pme_en
|
|
U2EN, 1 //bit4 u2_pme_en
|
|
}
|
|
|
|
Method (_PS3, 0, NotSerialized)
|
|
{
|
|
Store (One, CPME)
|
|
Store (One, U2EN)
|
|
Store (One, U3EN)
|
|
|
|
\_SB.CSD3(MODPHY_SPD_GATING_XDCI)
|
|
}
|
|
Method (_PS0, 0, NotSerialized)
|
|
{
|
|
Store (Zero, CPME)
|
|
Store (Zero, U2EN)
|
|
Store (Zero, U3EN)
|
|
|
|
If(LEqual(DVID,0xFFFF)) {
|
|
Return()
|
|
}
|
|
|
|
\_SB.CSD0(MODPHY_SPD_GATING_XDCI)
|
|
}
|
|
|
|
Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
|
|
{
|
|
Return (Zero)
|
|
}
|
|
|
|
Method (_PR3, 0, NotSerialized) // _PR3: Power Resources for D3hot
|
|
{
|
|
Return (Package (0x01)
|
|
{
|
|
USBC // return dummy package
|
|
})
|
|
}
|
|
} // Scope(\_SB.PC00.XDCI)
|
|
} // XDCE
|
|
//
|
|
// XDCI - end
|
|
//
|
|
|
|
//
|
|
// USB - END
|
|
//
|
|
|
|
If (LNotEqual(GBES,0)) {
|
|
Scope(\_SB.PC00.GLAN)
|
|
{
|
|
Method (_PS3, 0, NotSerialized)
|
|
{
|
|
\_SB.CSD3(MODPHY_SPD_GATING_GBE)
|
|
}
|
|
Method (_PS0, 0, NotSerialized)
|
|
{
|
|
If(LNot(GBED)){ // If GBE_FDIS_PMC == 0
|
|
\_SB.CSD0(MODPHY_SPD_GATING_GBE)
|
|
}
|
|
}
|
|
} // Scope(\_SB.PC00.GLAN)
|
|
}
|
|
|
|
//
|
|
// Human Interface Devices Start
|
|
//
|
|
|
|
//
|
|
//
|
|
// PCH I2C1 - TouchPanel Power control
|
|
//
|
|
Scope(\_SB.PC00.I2C1){
|
|
/// PS0X Method, called by PS0 method in PchSerialIo.asl
|
|
Method(PS0X,0,Serialized)
|
|
{
|
|
}
|
|
/// PS3X Method, called by PS3 method in PchSerialIo.asl
|
|
Method(PS3X,0,Serialized)
|
|
{
|
|
}
|
|
/// \ref i2c1_pr_pxtc
|
|
///@defgroup I2C1_scope I2C1 Scope
|
|
PowerResource(PXTC, 0, 0){
|
|
Method(_STA){
|
|
Return(PSTA())
|
|
}
|
|
|
|
Method(_ON){
|
|
PON()
|
|
}
|
|
|
|
Method(_OFF){
|
|
POFF()
|
|
}
|
|
} // End PXTC
|
|
/// Variable:
|
|
Name(ONTM, 0) ///ONTM: 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON
|
|
Method(PSTA){
|
|
If(LEqual(\_SB.GGOV(GPLP),1)) {
|
|
Return(0x01)
|
|
} Else {
|
|
Return(0x00)
|
|
}
|
|
}
|
|
|
|
// Timing of Power and Reset for I2C Touch Panel
|
|
// _____________________________________________________________________________________________________
|
|
// | minimum required time | Reset de-assert from Power On (ms) | Power Off from Reset assert (ms)|
|
|
// |_______________________|_______________________________________|_____________________________________|
|
|
// | current setting | 2 | 3 |
|
|
// |_______________________|_______________________________________|_____________________________________|
|
|
// * no maximum time limitation.
|
|
|
|
Method(PON, 0) /// _ON Method \n Turn on
|
|
{
|
|
// drive pwr high
|
|
\_SB.SGOV(GPLP, PPLP)
|
|
Sleep(2) // time for Reset de-assert from Power On
|
|
// De-Assert GPIO RST
|
|
\_SB.SGOV(GPLR, PPLR)
|
|
// update ONTM
|
|
Store(Timer(), ONTM)
|
|
// enable int line
|
|
\_SB.SGRA(GPLI, PPLI)
|
|
}
|
|
Method(POFF, 0) /// _OFF method \n Turn off
|
|
{
|
|
// disable int line
|
|
Xor(PPLI, 1, Local0)
|
|
\_SB.SGRA(GPLI, Local0)
|
|
// Assert GPIO RST
|
|
Xor(PPLR, 1, Local0)
|
|
\_SB.SGOV(GPLR, Local0)
|
|
Sleep(3) // time for Power Off from Reset assert
|
|
// drive pwr low
|
|
Xor(PPLP, 1, Local0)
|
|
\_SB.SGOV(GPLP, Local0)
|
|
// update ONTM
|
|
Store(Zero , ONTM) ///- Clear ONTM
|
|
}
|
|
|
|
Scope(TPL1){
|
|
Name (TD_P, Package(){\_SB.PC00.I2C1.PXTC}) // TD_P - Touch Device Power Package
|
|
|
|
Alias(IC1D, TD_D) // TD_D - Touch Device power on delay
|
|
Alias(\_SB.PC00.I2C1.ONTM, TD_C) // TD_C - Touch Device I2C controller power on timestamp
|
|
|
|
Include("Rtd3I2cTouchDev.asl")
|
|
Method(_PS0) { PS0X() }
|
|
Method(_PS3) { PS3X() }
|
|
}// End Of Scope(TPL1)
|
|
|
|
}// Scope(\_SB.PC00.I2C1)
|
|
|
|
//
|
|
//Power Resource for Audio Codec
|
|
Scope(\_SB.PC00)
|
|
{
|
|
PowerResource(PAUD, 0, 0) {
|
|
/// Namespace variable used:
|
|
Name(PSTA, One) /// PSTA: Physical Power Status of Codec 0 - OFF; 1-ON
|
|
Name(ONTM, Zero) /// ONTM: 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON
|
|
|
|
Name(_STA, One) /// _STA: PowerResource Logical Status 0 - OFF; 1-ON
|
|
|
|
///@defgroup pr_paud Power Resource for onboard Audio CODEC
|
|
|
|
Method(_ON, 0){ /// _ON method \n
|
|
Store(One, _STA) ///- Set Logocal power state
|
|
PUAM() ///- Call PUAM() to tansition Physical state to match current logical state
|
|
///@addtogroup pr_paud
|
|
} // End _ON
|
|
|
|
Method(_OFF, 0){ /// _OFF method \n
|
|
Store(Zero, _STA) ///- Set the current power state
|
|
PUAM() ///- Call PUAM() to tansition Physical state to match current logical state
|
|
///@addtogroup pr_paud
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} // End _OFF
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/// PUAM - Power Resource User Absent Mode for onboard Audio CODEC
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/// Arguments:
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///
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/// Uses:
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/// _STA - Variable updated by Power Resource _ON/_OFF methods \n
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/// \\UAMS - Variable updated by GUAM method to show User absent present \n
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/// ONTM - Local variable to store ON time during Speculative ON \n
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/// ______________________________
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// | Inputs | Outputs |
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// ______________________________
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// | _STA | \UAMS | GPIO | ONTM |
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// ______________________________
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// | 1 | 0 | ON | !0 |
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// | 1 | !0 | ON | !0 |
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// | 0 | 0 | ON | !0 |
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// | 0 | !0 | OFF | 0 |
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// ______________________________
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/**
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<table>
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<tr> <th colspan="2"> Inputs <th colspan="2"> Output
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<tr> <th>_STA <th> \\UAMS <th> GPIO <th>ONTM
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<tr> <td>1 <td>0 <td>ON <td>!0
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<tr> <td>1 <td>!0<td>ON <td>!0
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<tr> <td>0 <td>0 <td>ON <td>!0
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<tr> <td>0 <td>!0<td>OFF<td> 0
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</table>
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**/
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///@addtogroup pr_paud_puam
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Method(PUAM, 0, Serialized)
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{
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// power rail = NOT there for ICL U
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// Note:- Audio Power enable need not be implemented by default and need rework if we need power control.
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If (LAnd(LEqual(^_STA, Zero), LNotEqual(\UAMS, Zero))) { ///New state = OFF Check if (_STA ==0 && \UAMS != 0) \n
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} Else { /// New state = ON (_STA=1) or (_STA=0 and \UAMS=0)
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/// Turn power on \n
|
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If(LNotEqual(^PSTA, One)) { ///- Skip below if Power Resource is already in ON
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|
Store(One, ^PSTA) ///- >> Set PSTA to 1
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Store(Timer(), ^ONTM) ///- >> Start the timer for this PR
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}
|
|
}
|
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///@defgroup pr_paud_puam Power Resource User Absent Mode for onboard Audio CODEC
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} //PUAM
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|
} //PAUD
|
|
} //Scope(\_SB.PC00)
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|
|
|
//
|
|
// Check HDAS (HD-Audio) controller present
|
|
//
|
|
If(LNotEqual(\_SB.PC00.HDAS.VDID, 0xFFFFFFFF)) {
|
|
Scope(\_SB.PC00.HDAS) {
|
|
Method(PS0X,0,Serialized) /// Platform D0 Method for HD-A Controller
|
|
{
|
|
If(LEqual(\_SB.PC00.PAUD.ONTM, Zero)){ ///- Check if ONTM=0
|
|
Return()
|
|
}
|
|
|
|
///
|
|
///- Make sure "D0 delay" (AUDD) delay is elapsed before returning _PS0
|
|
///- Local0: Elapse time since the _ON method
|
|
///- VRRD: VR Rampup Delay
|
|
///- AUDD: Time required for device to be ready after power on
|
|
///- Local1 = AUDD + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay
|
|
///- So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method
|
|
///
|
|
Divide(Subtract(Timer(), \_SB.PC00.PAUD.ONTM), 10000, , Local0) ///- Store Elapsed time in ms, ignore remainder
|
|
Add(AUDD, VRRD, Local1) ///- Incorporate VR Rampup Delay
|
|
If(LLess(Local0, Local1)) { ///- Do not sleep if already past the delay requirement audio
|
|
///- Delay for device init
|
|
Sleep(Subtract(Local1, Local0)) ///- Sleep (AUDD + VRRD - time elapsed)
|
|
}
|
|
}
|
|
|
|
///Associate _PR0 with \ref pr_paud
|
|
Name(_PR0, Package(){\_SB.PC00.PAUD})
|
|
///@defgroup hdef_scope Intel High Definition Audio Scope
|
|
}
|
|
}// If(LNotEqual(\_SB.PC00.HDAS.VDID, 0xFFFFFFFF))
|
|
//GPE Event handling - Start
|
|
Scope(\_GPE) {
|
|
//
|
|
// Alternate _L6F(), to handle 2-tier RTD3 GPE events here
|
|
//
|
|
Method(AL6F) {
|
|
// X4 PCIe Connector (SLOT1) wake event
|
|
If (\_SB.ISME(PSWP))
|
|
{
|
|
\_SB.SHPO(PSWP, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
|
|
Notify(\_SB.PC00.RP21, 0x02) // device wake
|
|
\_SB.CAGS(PSWP)
|
|
}
|
|
|
|
//X4 PCIe Connector (SLOT2) wake event
|
|
If (\_SB.ISME(PSW2))
|
|
{
|
|
\_SB.SHPO(PSW2, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
|
|
Notify(\_SB.PC00.RP09, 0x02) // device wake
|
|
\_SB.CAGS(PSW2) // Clear GPE event status
|
|
}
|
|
|
|
//X2 PCIe Connector (SLOT3) wake event
|
|
If (\_SB.ISME(PSW3))
|
|
{
|
|
\_SB.SHPO(PSW3, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
|
|
Notify(\_SB.PC00.RP05, 0x02) // device wake
|
|
\_SB.CAGS(PSW3) // Clear GPE event status
|
|
}
|
|
|
|
// WLAN wake event
|
|
If (\_SB.ISME(WLWK))
|
|
{
|
|
\_SB.SHPO(WLWK, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
|
|
Notify(\_SB.PC00.RP08, 0x02) // device wake
|
|
\_SB.CAGS(WLWK) // WIFI_WAKE_N
|
|
}
|
|
#ifndef PCH_ADPP
|
|
// Onboard MR 1 wake event
|
|
If (\_SB.ISME(OMW1))
|
|
{
|
|
\_SB.SHPO(OMW1, 1) // set gpio ownership to driver(0=ACPI mode, 1=GPIO mode)
|
|
Notify(\_SB.PC00.RP25, 0x02) // device wake
|
|
\_SB.CAGS(OMW1)
|
|
}
|
|
#endif
|
|
}
|
|
} //Scope(\_GPE)
|
|
//GPE Event handling - End
|
|
} // End SSDT
|