184 lines
5.1 KiB
Plaintext
184 lines
5.1 KiB
Plaintext
/** @file
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Global power removal veto tracker
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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// Global mask to track PS_ON consent from IPs.
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// Bit: 0 - SATA, 1 - PCIe Aux Power, 2 - TCSS PD, 3 - Windows Standby, 4 - PCIe CEM D3cold
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Name(GPOM, 0x8) // Stanby bit value -by default veto
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//
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// Global power removal veto tracker. Gathers information from all IPs about power
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// removal consent.
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// Arg0 - Interface index, 0 - SATA, 1 - PCIe Aux Power, 2 - TCSS PD, 3 - Windows Standby, 4 - PCIe CEM D3cold
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// Arg1 - 0: Allow power removal, 1: veto power removal
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//
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Method(GPRV, 2, Serialized) {
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ShiftLeft(0x1, Arg0, Local0)
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If(Arg1) {
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Or(\GPOM, Local0, \GPOM)
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} Else {
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And(\GPOM, Not(Local0), \GPOM)
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}
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If(LEqual(\GPOM, 0)) {
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\PSOC(1)
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} Else {
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\PSOC(0)
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}
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}
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Name(PCPB, 0x0) // PCIe core power veto bitmask, default - allow for core power removal
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//
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// CEM PCIE slots core power removal permission
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// aggregation.
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// Arg0 - PCIe index in the aggregation bitmask
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// Indexing:
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// 0 - PCH slot1
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// 1 - PCH slot2
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// 2 - PCH slot3
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// 3 - PEG slot1
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// 4 - PEG slot2
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// Arg1 - 0: agree to core power down, 1: veto core power down
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Method(PCPA, 2, Serialized) {
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ShiftLeft(0x1, Arg0, Local0)
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If(Arg1) {
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Or(\PCPB, Local0, \PCPB)
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} Else {
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And(\PCPB, Not(Local0), \PCPB)
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}
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If(LEqual(PCPB, 0)) {
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\GPRV(1, 0)
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} Else {
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\GPRV(1, 1)
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}
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}
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Name(RPSM, 0x0) // PCIe CEM Slot D3cold aggregation status bitmask, default - All enter D3cold
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//
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// CEM PCIE slots D3cold permission for PS_ON
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// Arg0 - CEM PCIe slot index in the D3cold aggregation status bitmask
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// Indexing:
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// 0 - PCH slot1
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// 1 - PCH slot2
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// 2 - PCH slot3
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// 3 - PEG slot1
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// 4 - PEG slot2
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// Arg1 - 0: enter D3cold, 1: leave D3cold
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Method(RPSC, 2, Serialized) {
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ShiftLeft(0x1, Arg0, Local0)
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If(Arg1) {
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Or(\RPSM, Local0, \RPSM)
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} Else {
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And(\RPSM, Not(Local0), \RPSM)
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}
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If(LEqual(\RPSM, 0)) {
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\GPRV(4, 0)
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} Else {
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\GPRV(4, 1)
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}
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}
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Name(SATM, 0) // SATA ports disable bitmask. Each bit represents SATA port.
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//
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// Update SATA bitmask that allow for PS_ON entry
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// Arg0 - SATA port index
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// Arg1 - 0: SATA disable, 1: SATA enable
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//
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Method(STMC, 2, Serialized) {
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//
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// This is just to clear the junk values on SATM variables since it might be modified
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// unexpectedly by RST driver via _DSM method.
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//
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And(\SATM, SPPR, Local0)
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Store (Local0, SATM)
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ShiftLeft(0x1, Arg0, Local0)
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If(Arg1) {
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Or(\SATM, Local0, \SATM)
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} Else {
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And(\SATM, Not(Local0), \SATM)
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}
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If(LEqual(\SATM, 0)) {
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\GPRV(0,0)
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} Else {
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\GPRV(0,1)
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}
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}
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//
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// Get the SATA port status in the mask
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// Arg0 - SATA port index
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// @return 0: SATA disabled, 1: SATA enabled
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//
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Method(STMS, 1, Serialized) {
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ShiftLeft(0x1, Arg0, Local0)
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And(Local0, \SATM, Local1)
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If(Local1) {
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Return(1)
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} Else {
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Return(0)
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}
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}
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//
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// PCIe power budgeting support.
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//
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External(\AUPL) // Auxilary power limit
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Name(AURB, 0xFFFFFFFF) // Auxilary power remaining budget. Initialized on demand to \AUPL value by budgeting method.
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//
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// Reserve auxilary power budget.
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// Arg0 - 0: release, 1: reserve
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// Arg1 - power in mW
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//
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// @retval 0 - Request denied, remaining power not updated
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// @retval 1 - Request accepted, remaining power updated
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//
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Method(RAPC, 2, Serialized) {
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If(LEqual(\AURB, 0xFFFFFFFF)) {
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Store(\AUPL, \AURB)
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}
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If(Arg0) {
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If(LGreaterEqual(\AURB, Arg1)) {
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Subtract(\AURB, Arg1, \AURB)
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Return(1)
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} Else {
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Return(0)
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}
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} Else {
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Add(Arg1, \AURB, \AURB)
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Return(1)
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}
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} //End of RAPC
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