1387 lines
39 KiB
Plaintext
1387 lines
39 KiB
Plaintext
/** @file
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ACPI DSDT table
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2018 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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// General Purpose Events. This Scope handles the Run-time and
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// Wake-time SCIs. The specific method called will be determined by
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// the _Lxx value, where xx equals the bit location in the General
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// Purpose Event register(s).
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External(\_SB.PC00.MC, DeviceObj)
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External(\_SB.PC00.MC.D1F0, FieldUnitObj)
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External(\_SB.PC00.MC.D1F1, FieldUnitObj)
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External(\_SB.PC00.MC.D6F0, FieldUnitObj)
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External(\_SB.PC00.PEG0.HPME, MethodObj)
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External(\_SB.PC00.PEG1.HPME, MethodObj)
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External(\_SB.PC00.PEG2.HPME, MethodObj)
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External(\_SB.PC00.PEG3.HPME, MethodObj)
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External(\_GPE.AL6F, MethodObj)
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External(\_GPE.P0L6, MethodObj)
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External(\_GPE.P1L6, MethodObj)
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External(\_GPE.P2L6, MethodObj)
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External(\_GPE.P3L6, MethodObj)
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External(SGGP)
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External(P1GP)
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External(P2GP)
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External(P3GP)
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External(P0WK)
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External(P1WK)
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External(P2WK)
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External(P3WK)
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External(\_SB.PC00.TRP0.VDID)
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External(\_SB.PC00.TRP0.PDCX)
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External(\_SB.PC00.TRP0.PDSX)
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External(\_SB.PC00.TRP0.L0SE)
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External(\_SB.PC00.TRP1.VDID)
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External(\_SB.PC00.TRP1.PDCX)
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External(\_SB.PC00.TRP1.PDSX)
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External(\_SB.PC00.TRP1.L0SE)
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External(\_SB.PC00.TRP2.VDID)
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External(\_SB.PC00.TRP2.PDCX)
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External(\_SB.PC00.TRP2.PDSX)
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External(\_SB.PC00.TRP2.L0SE)
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External(\_SB.PC00.TRP3.VDID)
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External(\_SB.PC00.TRP3.PDCX)
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External(\_SB.PC00.TRP3.PDSX)
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External(\_SB.PC00.TRP3.L0SE)
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External(\_SB.PC00.TRP4.VDID)
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External(\_SB.PC00.TRP4.PDCX)
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External(\_SB.PC00.TRP4.PDSX)
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External(\_SB.PC00.TRP4.L0SE)
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External(\_SB.PC00.TRP5.VDID)
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External(\_SB.PC00.TRP5.PDCX)
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External(\_SB.PC00.TRP5.PDSX)
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External(\_SB.PC00.TRP5.L0SE)
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External(\_SB.PC01.TRP0.VDID)
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External(\_SB.PC01.TRP0.PDCX)
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External(\_SB.PC01.TRP0.PDSX)
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External(\_SB.PC01.TRP0.L0SE)
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External(\_SB.PC01.TRP1.VDID)
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External(\_SB.PC01.TRP1.PDCX)
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External(\_SB.PC01.TRP1.PDSX)
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External(\_SB.PC01.TRP1.L0SE)
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External(\_SB.PC01.TRP2.VDID)
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External(\_SB.PC01.TRP2.PDCX)
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External(\_SB.PC01.TRP2.PDSX)
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External(\_SB.PC01.TRP2.L0SE)
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External(\_SB.PC01.TRP3.VDID)
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External(\_SB.PC01.TRP3.PDCX)
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External(\_SB.PC01.TRP3.PDSX)
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External(\_SB.PC01.TRP3.L0SE)
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External(\_SB.PC01.TRP4.VDID)
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External(\_SB.PC01.TRP4.PDCX)
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External(\_SB.PC01.TRP4.PDSX)
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External(\_SB.PC01.TRP4.L0SE)
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External(\_SB.PC01.TRP5.VDID)
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External(\_SB.PC01.TRP5.PDCX)
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External(\_SB.PC01.TRP5.PDSX)
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External(\_SB.PC01.TRP5.L0SE)
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Scope(\_GPE)
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{
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// Note:
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// Originally, the two GPE methods below are automatically generated, but, for ASL code restructuring,
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// disabled the automatic generation and declare the ASL code here.
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//
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//
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// This PME event (PCH's GPE 69h) is received on one or more of the PCI Express* ports or
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// an assert PMEGPE message received via DMI
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//
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Method(_L69, 0, serialized) {
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\_SB.PC00.RP01.HPME()
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\_SB.PC00.RP02.HPME()
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\_SB.PC00.RP03.HPME()
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\_SB.PC00.RP04.HPME()
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\_SB.PC00.RP05.HPME()
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\_SB.PC00.RP06.HPME()
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\_SB.PC00.RP07.HPME()
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\_SB.PC00.RP08.HPME()
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\_SB.PC00.RP09.HPME()
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\_SB.PC00.RP10.HPME()
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\_SB.PC00.RP11.HPME()
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\_SB.PC00.RP12.HPME()
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\_SB.PC00.RP13.HPME()
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\_SB.PC00.RP14.HPME()
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\_SB.PC00.RP15.HPME()
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\_SB.PC00.RP16.HPME()
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\_SB.PC00.RP17.HPME()
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\_SB.PC00.RP18.HPME()
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\_SB.PC00.RP19.HPME()
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\_SB.PC00.RP20.HPME()
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\_SB.PC00.RP21.HPME()
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\_SB.PC00.RP22.HPME()
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\_SB.PC00.RP23.HPME()
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\_SB.PC00.RP24.HPME()
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If (CondRefOf(\_SB.PC00.MC)) {
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If(LEqual(\_SB.PC00.MC.D6F0,1))
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{
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\_SB.PC00.PEG0.HPME()
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Notify(\_SB.PC00.PEG0, 0x02)
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Notify(\_SB.PC00.PEG0.PEGP, 0x02)
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}
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If(LEqual(\_SB.PC00.MC.D1F0,1))
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{
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\_SB.PC00.PEG1.HPME()
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Notify(\_SB.PC00.PEG1, 0x02)
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}
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If(LEqual(\_SB.PC00.MC.D1F1,1))
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{
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\_SB.PC00.PEG2.HPME()
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Notify(\_SB.PC00.PEG2, 0x02)
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}
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}
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}
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// PCI Express Hot-Plug caused the wake event.
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Method(_L61)
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{
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Add(L01C,1,L01C) // Increment L01 Entry Count.
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P8XH(0,0x01) // Output information to Port 80h.
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P8XH(1,L01C)
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// Check Root Port 1 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP01.VDID,0xFFFFFFFF),\_SB.PC00.RP01.HPSX))
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{
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If(\_SB.PC00.RP01.PDCX)
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{
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// Clear all status bits first.
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Store(1,\_SB.PC00.RP01.PDCX)
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Store(1,\_SB.PC00.RP01.HPSX)
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//
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// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
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// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
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// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
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// disabled on empty slots prior booting to OS.
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//
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If(LNot(\_SB.PC00.RP01.PDSX)) {
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// The PCI Express slot is empty, so disable L0s on hot unplug
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//
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Store(0,\_SB.PC00.RP01.L0SE)
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}
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}
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Else
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{
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// False event. Clear Hot-Plug Status
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// then exit.
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Store(1,\_SB.PC00.RP01.HPSX)
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}
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}
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// Check Root Port 2 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP02.VDID,0xFFFFFFFF),\_SB.PC00.RP02.HPSX))
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{
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If(\_SB.PC00.RP02.PDCX)
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{
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Store(1,\_SB.PC00.RP02.PDCX)
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Store(1,\_SB.PC00.RP02.HPSX)
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If(LNot(\_SB.PC00.RP02.PDSX)) {
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Store(0,\_SB.PC00.RP02.L0SE)
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}
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}
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Else
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{
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Store(1,\_SB.PC00.RP02.HPSX)
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}
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}
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// Check Root Port 3 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP03.VDID,0xFFFFFFFF),\_SB.PC00.RP03.HPSX))
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{
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If(\_SB.PC00.RP03.PDCX)
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{
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Store(1,\_SB.PC00.RP03.PDCX)
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Store(1,\_SB.PC00.RP03.HPSX)
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If(LNot(\_SB.PC00.RP03.PDSX)) {
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Store(0,\_SB.PC00.RP03.L0SE)
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}
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}
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Else
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{
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Store(1,\_SB.PC00.RP03.HPSX)
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}
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}
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// Check Root Port 4 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP04.VDID,0xFFFFFFFF),\_SB.PC00.RP04.HPSX))
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{
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If(\_SB.PC00.RP04.PDCX)
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{
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Store(1,\_SB.PC00.RP04.PDCX)
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Store(1,\_SB.PC00.RP04.HPSX)
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If(LNot(\_SB.PC00.RP04.PDSX)) {
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Store(0,\_SB.PC00.RP04.L0SE)
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}
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}
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Else
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{
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Store(1,\_SB.PC00.RP04.HPSX)
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}
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}
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// Check Root Port 5 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP05.VDID,0xFFFFFFFF),\_SB.PC00.RP05.HPSX))
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{
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If(\_SB.PC00.RP05.PDCX)
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{
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Store(1,\_SB.PC00.RP05.PDCX)
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Store(1,\_SB.PC00.RP05.HPSX)
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If(LNot(\_SB.PC00.RP05.PDSX)) {
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Store(0,\_SB.PC00.RP05.L0SE)
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}
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}
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Else
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{
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Store(1,\_SB.PC00.RP05.HPSX)
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}
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}
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// Check Root Port 6 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP06.VDID,0xFFFFFFFF),\_SB.PC00.RP06.HPSX))
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{
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If(\_SB.PC00.RP06.PDCX)
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{
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Store(1,\_SB.PC00.RP06.PDCX)
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Store(1,\_SB.PC00.RP06.HPSX)
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If(LNot(\_SB.PC00.RP06.PDSX)) {
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Store(0,\_SB.PC00.RP06.L0SE)
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}
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}
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Else
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{
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Store(1,\_SB.PC00.RP06.HPSX)
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}
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}
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// Check Root Port 7 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP07.VDID,0xFFFFFFFF),\_SB.PC00.RP07.HPSX))
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{
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If(\_SB.PC00.RP07.PDCX)
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{
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Store(1,\_SB.PC00.RP07.PDCX)
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Store(1,\_SB.PC00.RP07.HPSX)
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If(LNot(\_SB.PC00.RP07.PDSX)) {
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Store(0,\_SB.PC00.RP07.L0SE)
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}
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If(LEqual(PFLV,FlavorDesktop))
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{
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}
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Else
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{
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If (\ECON)
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{
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//@todo: Waiting for DOCK offect data
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// If(LEqual(\_SB.PC00.LPCB.H_EC.ECRD(RefOf(\_SB.PC00.LPCB.H_EC.DOCK)), 0))
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// { // If not docked then it's hot plug
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// }
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}
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}
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}
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Else
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{
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Store(1,\_SB.PC00.RP07.HPSX)
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}
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}
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// Check Root Port 8 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP08.VDID,0xFFFFFFFF),\_SB.PC00.RP08.HPSX))
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{
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If(\_SB.PC00.RP08.PDCX)
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{
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Store(1,\_SB.PC00.RP08.PDCX)
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Store(1,\_SB.PC00.RP08.HPSX)
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If(LNot(\_SB.PC00.RP08.PDSX)) {
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Store(0,\_SB.PC00.RP08.L0SE)
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}
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If(LEqual(PFLV,FlavorDesktop))
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{
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}
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Else
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{
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If (\ECON)
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{
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//@todo: Waiting for DOCK offect data
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// If(LEqual(\_SB.PC00.LPCB.H_EC.ECRD(RefOf(\_SB.PC00.LPCB.H_EC.DOCK)), 0))
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// { // If not docked then it's hot plug
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// }
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}
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}
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}
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Else
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{
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Store(1,\_SB.PC00.RP08.HPSX)
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}
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}
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// Check Root Port 9 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP09.VDID,0xFFFFFFFF),\_SB.PC00.RP09.HPSX))
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{
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If(\_SB.PC00.RP09.PDCX)
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{
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Store(1,\_SB.PC00.RP09.PDCX)
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Store(1,\_SB.PC00.RP09.HPSX)
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If(LNot(\_SB.PC00.RP09.PDSX)) {
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Store(0,\_SB.PC00.RP09.L0SE)
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}
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}
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Else
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{
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Store(1,\_SB.PC00.RP09.HPSX)
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}
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}
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// Check Root Port 10 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP10.VDID,0xFFFFFFFF),\_SB.PC00.RP10.HPSX))
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{
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If(\_SB.PC00.RP10.PDCX)
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{
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Store(1,\_SB.PC00.RP10.PDCX)
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Store(1,\_SB.PC00.RP10.HPSX)
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If(LNot(\_SB.PC00.RP10.PDSX)) {
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Store(0,\_SB.PC00.RP10.L0SE)
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}
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}
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Else
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{
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Store(1,\_SB.PC00.RP10.HPSX)
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}
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}
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// Check Root Port 11 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP11.VDID,0xFFFFFFFF),\_SB.PC00.RP11.HPSX))
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{
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If(\_SB.PC00.RP11.PDCX)
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{
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Store(1,\_SB.PC00.RP11.PDCX)
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Store(1,\_SB.PC00.RP11.HPSX)
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If(LNot(\_SB.PC00.RP11.PDSX)) {
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Store(0,\_SB.PC00.RP11.L0SE)
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}
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}
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Else
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{
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Store(1,\_SB.PC00.RP11.HPSX)
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}
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}
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// Check Root Port 12 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP12.VDID,0xFFFFFFFF),\_SB.PC00.RP12.HPSX))
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{
|
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If(\_SB.PC00.RP12.PDCX)
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{
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Store(1,\_SB.PC00.RP12.PDCX)
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Store(1,\_SB.PC00.RP12.HPSX)
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If(LNot(\_SB.PC00.RP12.PDSX)) {
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Store(0,\_SB.PC00.RP12.L0SE)
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}
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}
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Else
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{
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Store(1,\_SB.PC00.RP12.HPSX)
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}
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}
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// Check Root Port 13 for a Hot Plug Event if the Port is
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// enabled.
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If(LAnd(LNotEqual(\_SB.PC00.RP13.VDID,0xFFFFFFFF),\_SB.PC00.RP13.HPSX))
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{
|
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If(\_SB.PC00.RP13.PDCX)
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{
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Store(1,\_SB.PC00.RP13.PDCX)
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Store(1,\_SB.PC00.RP13.HPSX)
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If(LNot(\_SB.PC00.RP13.PDSX)) {
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Store(0,\_SB.PC00.RP13.L0SE)
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}
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}
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Else
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{
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Store(1,\_SB.PC00.RP13.HPSX)
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}
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}
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// Check Root Port 14 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.RP14.VDID,0xFFFFFFFF),\_SB.PC00.RP14.HPSX))
|
|
{
|
|
If(\_SB.PC00.RP14.PDCX)
|
|
{
|
|
Store(1,\_SB.PC00.RP14.PDCX)
|
|
Store(1,\_SB.PC00.RP14.HPSX)
|
|
|
|
If(LNot(\_SB.PC00.RP14.PDSX)) {
|
|
Store(0,\_SB.PC00.RP14.L0SE)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Store(1,\_SB.PC00.RP14.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check Root Port 15 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.RP15.VDID,0xFFFFFFFF),\_SB.PC00.RP15.HPSX))
|
|
{
|
|
If(\_SB.PC00.RP15.PDCX)
|
|
{
|
|
Store(1,\_SB.PC00.RP15.PDCX)
|
|
Store(1,\_SB.PC00.RP15.HPSX)
|
|
|
|
If(LNot(\_SB.PC00.RP15.PDSX)) {
|
|
Store(0,\_SB.PC00.RP15.L0SE)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Store(1,\_SB.PC00.RP15.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check Root Port 16 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.RP16.VDID,0xFFFFFFFF),\_SB.PC00.RP16.HPSX))
|
|
{
|
|
If(\_SB.PC00.RP16.PDCX)
|
|
{
|
|
Store(1,\_SB.PC00.RP16.PDCX)
|
|
Store(1,\_SB.PC00.RP16.HPSX)
|
|
|
|
If(LNot(\_SB.PC00.RP16.PDSX)) {
|
|
Store(0,\_SB.PC00.RP16.L0SE)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Store(1,\_SB.PC00.RP16.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check Root Port 17 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.RP17.VDID,0xFFFFFFFF),\_SB.PC00.RP17.HPSX))
|
|
{
|
|
If(\_SB.PC00.RP17.PDCX)
|
|
{
|
|
Store(1,\_SB.PC00.RP17.PDCX)
|
|
Store(1,\_SB.PC00.RP17.HPSX)
|
|
|
|
If(LNot(\_SB.PC00.RP17.PDSX)) {
|
|
Store(0,\_SB.PC00.RP17.L0SE)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Store(1,\_SB.PC00.RP17.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check Root Port 18 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.RP18.VDID,0xFFFFFFFF),\_SB.PC00.RP18.HPSX))
|
|
{
|
|
If(\_SB.PC00.RP18.PDCX)
|
|
{
|
|
Store(1,\_SB.PC00.RP18.PDCX)
|
|
Store(1,\_SB.PC00.RP18.HPSX)
|
|
|
|
If(LNot(\_SB.PC00.RP18.PDSX)) {
|
|
Store(0,\_SB.PC00.RP18.L0SE)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Store(1,\_SB.PC00.RP18.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check Root Port 19 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.RP19.VDID,0xFFFFFFFF),\_SB.PC00.RP19.HPSX))
|
|
{
|
|
If(\_SB.PC00.RP19.PDCX)
|
|
{
|
|
Store(1,\_SB.PC00.RP19.PDCX)
|
|
Store(1,\_SB.PC00.RP19.HPSX)
|
|
|
|
If(LNot(\_SB.PC00.RP19.PDSX)) {
|
|
Store(0,\_SB.PC00.RP19.L0SE)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Store(1,\_SB.PC00.RP19.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check Root Port 20 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.RP20.VDID,0xFFFFFFFF),\_SB.PC00.RP20.HPSX))
|
|
{
|
|
If(\_SB.PC00.RP20.PDCX)
|
|
{
|
|
Store(1,\_SB.PC00.RP20.PDCX)
|
|
Store(1,\_SB.PC00.RP20.HPSX)
|
|
|
|
If(LNot(\_SB.PC00.RP20.PDSX)) {
|
|
Store(0,\_SB.PC00.RP20.L0SE)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Store(1,\_SB.PC00.RP20.HPSX)
|
|
}
|
|
}
|
|
// Check Root Port 21 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.RP21.VDID,0xFFFFFFFF),\_SB.PC00.RP21.HPSX))
|
|
{
|
|
If(\_SB.PC00.RP21.PDCX)
|
|
{
|
|
Store(1,\_SB.PC00.RP21.PDCX)
|
|
Store(1,\_SB.PC00.RP21.HPSX)
|
|
|
|
If(LNot(\_SB.PC00.RP21.PDSX)) {
|
|
Store(0,\_SB.PC00.RP21.L0SE)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Store(1,\_SB.PC00.RP21.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check Root Port 22 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.RP22.VDID,0xFFFFFFFF),\_SB.PC00.RP22.HPSX))
|
|
{
|
|
If(\_SB.PC00.RP22.PDCX)
|
|
{
|
|
Store(1,\_SB.PC00.RP22.PDCX)
|
|
Store(1,\_SB.PC00.RP22.HPSX)
|
|
|
|
If(LNot(\_SB.PC00.RP22.PDSX)) {
|
|
Store(0,\_SB.PC00.RP22.L0SE)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Store(1,\_SB.PC00.RP22.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check Root Port 23 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.RP23.VDID,0xFFFFFFFF),\_SB.PC00.RP23.HPSX))
|
|
{
|
|
If(\_SB.PC00.RP23.PDCX)
|
|
{
|
|
Store(1,\_SB.PC00.RP23.PDCX)
|
|
Store(1,\_SB.PC00.RP23.HPSX)
|
|
|
|
If(LNot(\_SB.PC00.RP23.PDSX)) {
|
|
Store(0,\_SB.PC00.RP23.L0SE)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Store(1,\_SB.PC00.RP23.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check Root Port 24 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.RP24.VDID,0xFFFFFFFF),\_SB.PC00.RP24.HPSX))
|
|
{
|
|
If(\_SB.PC00.RP24.PDCX)
|
|
{
|
|
Store(1,\_SB.PC00.RP24.PDCX)
|
|
Store(1,\_SB.PC00.RP24.HPSX)
|
|
|
|
If(LNot(\_SB.PC00.RP24.PDSX)) {
|
|
Store(0,\_SB.PC00.RP24.L0SE)
|
|
}
|
|
}
|
|
Else
|
|
{
|
|
Store(1,\_SB.PC00.RP24.HPSX)
|
|
}
|
|
}
|
|
//
|
|
// The iTBT PCIe Hot-Plug event
|
|
//
|
|
If (CondRefOf(\_SB.PC01)) {
|
|
// Check iTBT PCIe Root Port 0 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC01.TRP0.VDID,0xFFFFFFFF),\_SB.PC01.TRP0.HPSX))
|
|
{
|
|
// Delay for 100ms to meet the timing requirements
|
|
// of the PCI Express Base Specification, Revision
|
|
// 1.0A, Section 6.6 ("...software must wait at
|
|
// least 100ms from the end of reset of one or more
|
|
// device before it is permitted to issue
|
|
// Configuration Requests to those devices").
|
|
|
|
Sleep(100)
|
|
|
|
If(\_SB.PC01.TRP0.PDCX)
|
|
{
|
|
// Clear all status bits first.
|
|
|
|
Store(1,\_SB.PC01.TRP0.PDCX)
|
|
Store(1,\_SB.PC01.TRP0.HPSX)
|
|
|
|
//
|
|
// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
|
|
// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
|
|
// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
|
|
// disabled on empty slots prior booting to OS.
|
|
//
|
|
If(LNot(\_SB.PC01.TRP0.PDSX)) {
|
|
// The PCI Express slot is empty, so disable L0s on hot unplug
|
|
//
|
|
Store(0,\_SB.PC01.TRP0.L0SE)
|
|
|
|
}
|
|
// Call Handler for Bios assisted enumeration
|
|
// Handler uses syncronization algoritham to enumerate one Root port
|
|
// at a time
|
|
If(LEqual(ITBS, 1))
|
|
{
|
|
\_GPE.ITBT(0x00)
|
|
}
|
|
// Perform proper notification
|
|
// to the OS.
|
|
Notify(\_SB.PC01.TRP0,0)
|
|
}
|
|
Else
|
|
{
|
|
// False event. Clear Hot-Plug Status
|
|
// then exit.
|
|
|
|
Store(1,\_SB.PC01.TRP0.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check iTBT PCIe Root Port 1 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC01.TRP1.VDID,0xFFFFFFFF),\_SB.PC01.TRP1.HPSX))
|
|
{
|
|
// Delay for 100ms to meet the timing requirements
|
|
// of the PCI Express Base Specification, Revision
|
|
// 1.0A, Section 6.6 ("...software must wait at
|
|
// least 100ms from the end of reset of one or more
|
|
// device before it is permitted to issue
|
|
// Configuration Requests to those devices").
|
|
|
|
Sleep(100)
|
|
|
|
If(\_SB.PC01.TRP1.PDCX)
|
|
{
|
|
// Clear all status bits first.
|
|
|
|
Store(1,\_SB.PC01.TRP1.PDCX)
|
|
Store(1,\_SB.PC01.TRP1.HPSX)
|
|
|
|
//
|
|
// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
|
|
// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
|
|
// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
|
|
// disabled on empty slots prior booting to OS.
|
|
//
|
|
If(LNot(\_SB.PC01.TRP1.PDSX)) {
|
|
// The PCI Express slot is empty, so disable L0s on hot unplug
|
|
//
|
|
Store(0,\_SB.PC01.TRP1.L0SE)
|
|
|
|
}
|
|
// Call Handler for Bios assisted enumeration
|
|
// Handler uses syncronization algoritham to enumerate one Root port
|
|
// at a time
|
|
If(LEqual(ITBS, 1))
|
|
{
|
|
\_GPE.ITBT(0x01)
|
|
}
|
|
// Perform proper notification
|
|
// to the OS.
|
|
Notify(\_SB.PC01.TRP1,0)
|
|
}
|
|
Else
|
|
{
|
|
// False event. Clear Hot-Plug Status
|
|
// then exit.
|
|
|
|
Store(1,\_SB.PC01.TRP1.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check iTBT PCIe Root Port 2 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC01.TRP2.VDID,0xFFFFFFFF),\_SB.PC01.TRP2.HPSX))
|
|
{
|
|
// Delay for 100ms to meet the timing requirements
|
|
// of the PCI Express Base Specification, Revision
|
|
// 1.0A, Section 6.6 ("...software must wait at
|
|
// least 100ms from the end of reset of one or more
|
|
// device before it is permitted to issue
|
|
// Configuration Requests to those devices").
|
|
|
|
Sleep(100)
|
|
|
|
If(\_SB.PC01.TRP2.PDCX)
|
|
{
|
|
// Clear all status bits first.
|
|
|
|
Store(1,\_SB.PC01.TRP2.PDCX)
|
|
Store(1,\_SB.PC01.TRP2.HPSX)
|
|
|
|
//
|
|
// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
|
|
// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
|
|
// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
|
|
// disabled on empty slots prior booting to OS.
|
|
//
|
|
If(LNot(\_SB.PC01.TRP2.PDSX)) {
|
|
// The PCI Express slot is empty, so disable L0s on hot unplug
|
|
//
|
|
Store(0,\_SB.PC01.TRP2.L0SE)
|
|
|
|
}
|
|
// Call Handler for Bios assisted enumeration
|
|
// Handler uses syncronization algoritham to enumerate one Root port
|
|
// at a time
|
|
If(LEqual(ITBS, 1))
|
|
{
|
|
\_GPE.ITBT(0x02)
|
|
}
|
|
// Perform proper notification
|
|
// to the OS.
|
|
Notify(\_SB.PC01.TRP2,0)
|
|
}
|
|
Else
|
|
{
|
|
// False event. Clear Hot-Plug Status
|
|
// then exit.
|
|
|
|
Store(1,\_SB.PC01.TRP2.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check iTBT PCIe Root Port 3 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC01.TRP3.VDID,0xFFFFFFFF),\_SB.PC01.TRP3.HPSX))
|
|
{
|
|
// Delay for 100ms to meet the timing requirements
|
|
// of the PCI Express Base Specification, Revision
|
|
// 1.0A, Section 6.6 ("...software must wait at
|
|
// least 100ms from the end of reset of one or more
|
|
// device before it is permitted to issue
|
|
// Configuration Requests to those devices").
|
|
|
|
Sleep(100)
|
|
|
|
If(\_SB.PC01.TRP3.PDCX)
|
|
{
|
|
// Clear all status bits first.
|
|
|
|
Store(1,\_SB.PC01.TRP3.PDCX)
|
|
Store(1,\_SB.PC01.TRP3.HPSX)
|
|
|
|
//
|
|
// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
|
|
// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
|
|
// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
|
|
// disabled on empty slots prior booting to OS.
|
|
//
|
|
If(LNot(\_SB.PC01.TRP3.PDSX)) {
|
|
// The PCI Express slot is empty, so disable L0s on hot unplug
|
|
//
|
|
Store(0,\_SB.PC01.TRP3.L0SE)
|
|
|
|
}
|
|
// Call Handler for Bios assisted enumeration
|
|
// Handler uses syncronization algoritham to enumerate one Root port
|
|
// at a time
|
|
If(LEqual(ITBS, 1))
|
|
{
|
|
\_GPE.ITBT(0x03)
|
|
}
|
|
// Perform proper notification
|
|
// to the OS.
|
|
Notify(\_SB.PC01.TRP3,0)
|
|
}
|
|
Else
|
|
{
|
|
// False event. Clear Hot-Plug Status
|
|
// then exit.
|
|
|
|
Store(1,\_SB.PC01.TRP3.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check iTBT PCIe Root Port 4 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC01.TRP4.VDID,0xFFFFFFFF),\_SB.PC01.TRP4.HPSX))
|
|
{
|
|
// Delay for 100ms to meet the timing requirements
|
|
// of the PCI Express Base Specification, Revision
|
|
// 1.0A, Section 6.6 ("...software must wait at
|
|
// least 100ms from the end of reset of one or more
|
|
// device before it is permitted to issue
|
|
// Configuration Requests to those devices").
|
|
|
|
Sleep(100)
|
|
|
|
If(\_SB.PC01.TRP4.PDCX)
|
|
{
|
|
// Clear all status bits first.
|
|
|
|
Store(1,\_SB.PC01.TRP4.PDCX)
|
|
Store(1,\_SB.PC01.TRP4.HPSX)
|
|
|
|
//
|
|
// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
|
|
// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
|
|
// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
|
|
// disabled on empty slots prior booting to OS.
|
|
//
|
|
If(LNot(\_SB.PC01.TRP4.PDSX)) {
|
|
// The PCI Express slot is empty, so disable L0s on hot unplug
|
|
//
|
|
Store(0,\_SB.PC01.TRP4.L0SE)
|
|
|
|
}
|
|
// Call Handler for Bios assisted enumeration
|
|
// Handler uses syncronization algoritham to enumerate one Root port
|
|
// at a time
|
|
If(LEqual(ITBS, 1))
|
|
{
|
|
\_GPE.ITBT(0x04)
|
|
}
|
|
// Perform proper notification
|
|
// to the OS.
|
|
Notify(\_SB.PC01.TRP4,0)
|
|
}
|
|
Else
|
|
{
|
|
// False event. Clear Hot-Plug Status
|
|
// then exit.
|
|
|
|
Store(1,\_SB.PC01.TRP4.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check iTBT PCIe Root Port 5 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC01.TRP5.VDID,0xFFFFFFFF),\_SB.PC01.TRP5.HPSX))
|
|
{
|
|
// Delay for 100ms to meet the timing requirements
|
|
// of the PCI Express Base Specification, Revision
|
|
// 1.0A, Section 6.6 ("...software must wait at
|
|
// least 100ms from the end of reset of one or more
|
|
// device before it is permitted to issue
|
|
// Configuration Requests to those devices").
|
|
|
|
Sleep(100)
|
|
|
|
If(\_SB.PC01.TRP5.PDCX)
|
|
{
|
|
// Clear all status bits first.
|
|
|
|
Store(1,\_SB.PC01.TRP5.PDCX)
|
|
Store(1,\_SB.PC01.TRP5.HPSX)
|
|
|
|
//
|
|
// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
|
|
// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
|
|
// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
|
|
// disabled on empty slots prior booting to OS.
|
|
//
|
|
If(LNot(\_SB.PC01.TRP5.PDSX)) {
|
|
// The PCI Express slot is empty, so disable L0s on hot unplug
|
|
//
|
|
Store(0,\_SB.PC01.TRP5.L0SE)
|
|
|
|
}
|
|
// Call Handler for Bios assisted enumeration
|
|
// Handler uses syncronization algoritham to enumerate one Root port
|
|
// at a time
|
|
If(LEqual(ITBS, 1))
|
|
{
|
|
\_GPE.ITBT(0x05)
|
|
}
|
|
// Perform proper notification
|
|
// to the OS.
|
|
Notify(\_SB.PC01.TRP5,0)
|
|
}
|
|
Else
|
|
{
|
|
// False event. Clear Hot-Plug Status
|
|
// then exit.
|
|
|
|
Store(1,\_SB.PC01.TRP5.HPSX)
|
|
}
|
|
}
|
|
} Else {
|
|
// Check iTBT PCIe Root Port 0 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.TRP0.VDID,0xFFFFFFFF),\_SB.PC00.TRP0.HPSX))
|
|
{
|
|
// Delay for 100ms to meet the timing requirements
|
|
// of the PCI Express Base Specification, Revision
|
|
// 1.0A, Section 6.6 ("...software must wait at
|
|
// least 100ms from the end of reset of one or more
|
|
// device before it is permitted to issue
|
|
// Configuration Requests to those devices").
|
|
|
|
Sleep(100)
|
|
|
|
If(\_SB.PC00.TRP0.PDCX)
|
|
{
|
|
// Clear all status bits first.
|
|
|
|
Store(1,\_SB.PC00.TRP0.PDCX)
|
|
Store(1,\_SB.PC00.TRP0.HPSX)
|
|
|
|
//
|
|
// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
|
|
// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
|
|
// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
|
|
// disabled on empty slots prior booting to OS.
|
|
//
|
|
If(LNot(\_SB.PC00.TRP0.PDSX)) {
|
|
// The PCI Express slot is empty, so disable L0s on hot unplug
|
|
//
|
|
Store(0,\_SB.PC00.TRP0.L0SE)
|
|
|
|
}
|
|
// Call Handler for Bios assisted enumeration
|
|
// Handler uses syncronization algoritham to enumerate one Root port
|
|
// at a time
|
|
If(LEqual(ITBS, 1))
|
|
{
|
|
\_GPE.ITBT(0x00)
|
|
}
|
|
// Perform proper notification
|
|
// to the OS.
|
|
Notify(\_SB.PC00.TRP0,0)
|
|
}
|
|
Else
|
|
{
|
|
// False event. Clear Hot-Plug Status
|
|
// then exit.
|
|
|
|
Store(1,\_SB.PC00.TRP0.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check iTBT PCIe Root Port 1 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.TRP1.VDID,0xFFFFFFFF),\_SB.PC00.TRP1.HPSX))
|
|
{
|
|
// Delay for 100ms to meet the timing requirements
|
|
// of the PCI Express Base Specification, Revision
|
|
// 1.0A, Section 6.6 ("...software must wait at
|
|
// least 100ms from the end of reset of one or more
|
|
// device before it is permitted to issue
|
|
// Configuration Requests to those devices").
|
|
|
|
Sleep(100)
|
|
|
|
If(\_SB.PC00.TRP1.PDCX)
|
|
{
|
|
// Clear all status bits first.
|
|
|
|
Store(1,\_SB.PC00.TRP1.PDCX)
|
|
Store(1,\_SB.PC00.TRP1.HPSX)
|
|
|
|
//
|
|
// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
|
|
// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
|
|
// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
|
|
// disabled on empty slots prior booting to OS.
|
|
//
|
|
If(LNot(\_SB.PC00.TRP1.PDSX)) {
|
|
// The PCI Express slot is empty, so disable L0s on hot unplug
|
|
//
|
|
Store(0,\_SB.PC00.TRP1.L0SE)
|
|
|
|
}
|
|
// Call Handler for Bios assisted enumeration
|
|
// Handler uses syncronization algoritham to enumerate one Root port
|
|
// at a time
|
|
If(LEqual(ITBS, 1))
|
|
{
|
|
\_GPE.ITBT(0x01)
|
|
}
|
|
// Perform proper notification
|
|
// to the OS.
|
|
Notify(\_SB.PC00.TRP1,0)
|
|
}
|
|
Else
|
|
{
|
|
// False event. Clear Hot-Plug Status
|
|
// then exit.
|
|
|
|
Store(1,\_SB.PC00.TRP1.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check iTBT PCIe Root Port 2 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.TRP2.VDID,0xFFFFFFFF),\_SB.PC00.TRP2.HPSX))
|
|
{
|
|
// Delay for 100ms to meet the timing requirements
|
|
// of the PCI Express Base Specification, Revision
|
|
// 1.0A, Section 6.6 ("...software must wait at
|
|
// least 100ms from the end of reset of one or more
|
|
// device before it is permitted to issue
|
|
// Configuration Requests to those devices").
|
|
|
|
Sleep(100)
|
|
|
|
If(\_SB.PC00.TRP2.PDCX)
|
|
{
|
|
// Clear all status bits first.
|
|
|
|
Store(1,\_SB.PC00.TRP2.PDCX)
|
|
Store(1,\_SB.PC00.TRP2.HPSX)
|
|
|
|
//
|
|
// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
|
|
// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
|
|
// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
|
|
// disabled on empty slots prior booting to OS.
|
|
//
|
|
If(LNot(\_SB.PC00.TRP2.PDSX)) {
|
|
// The PCI Express slot is empty, so disable L0s on hot unplug
|
|
//
|
|
Store(0,\_SB.PC00.TRP2.L0SE)
|
|
|
|
}
|
|
// Call Handler for Bios assisted enumeration
|
|
// Handler uses syncronization algoritham to enumerate one Root port
|
|
// at a time
|
|
If(LEqual(ITBS, 1))
|
|
{
|
|
\_GPE.ITBT(0x02)
|
|
}
|
|
// Perform proper notification
|
|
// to the OS.
|
|
Notify(\_SB.PC00.TRP2,0)
|
|
}
|
|
Else
|
|
{
|
|
// False event. Clear Hot-Plug Status
|
|
// then exit.
|
|
|
|
Store(1,\_SB.PC00.TRP2.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check iTBT PCIe Root Port 3 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.TRP3.VDID,0xFFFFFFFF),\_SB.PC00.TRP3.HPSX))
|
|
{
|
|
// Delay for 100ms to meet the timing requirements
|
|
// of the PCI Express Base Specification, Revision
|
|
// 1.0A, Section 6.6 ("...software must wait at
|
|
// least 100ms from the end of reset of one or more
|
|
// device before it is permitted to issue
|
|
// Configuration Requests to those devices").
|
|
|
|
Sleep(100)
|
|
|
|
If(\_SB.PC00.TRP3.PDCX)
|
|
{
|
|
// Clear all status bits first.
|
|
|
|
Store(1,\_SB.PC00.TRP3.PDCX)
|
|
Store(1,\_SB.PC00.TRP3.HPSX)
|
|
|
|
//
|
|
// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
|
|
// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
|
|
// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
|
|
// disabled on empty slots prior booting to OS.
|
|
//
|
|
If(LNot(\_SB.PC00.TRP3.PDSX)) {
|
|
// The PCI Express slot is empty, so disable L0s on hot unplug
|
|
//
|
|
Store(0,\_SB.PC00.TRP3.L0SE)
|
|
|
|
}
|
|
// Call Handler for Bios assisted enumeration
|
|
// Handler uses syncronization algoritham to enumerate one Root port
|
|
// at a time
|
|
If(LEqual(ITBS, 1))
|
|
{
|
|
\_GPE.ITBT(0x03)
|
|
}
|
|
// Perform proper notification
|
|
// to the OS.
|
|
Notify(\_SB.PC00.TRP3,0)
|
|
}
|
|
Else
|
|
{
|
|
// False event. Clear Hot-Plug Status
|
|
// then exit.
|
|
|
|
Store(1,\_SB.PC00.TRP3.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check iTBT PCIe Root Port 4 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.TRP4.VDID,0xFFFFFFFF),\_SB.PC00.TRP4.HPSX))
|
|
{
|
|
// Delay for 100ms to meet the timing requirements
|
|
// of the PCI Express Base Specification, Revision
|
|
// 1.0A, Section 6.6 ("...software must wait at
|
|
// least 100ms from the end of reset of one or more
|
|
// device before it is permitted to issue
|
|
// Configuration Requests to those devices").
|
|
|
|
Sleep(100)
|
|
|
|
If(\_SB.PC00.TRP4.PDCX)
|
|
{
|
|
// Clear all status bits first.
|
|
|
|
Store(1,\_SB.PC00.TRP4.PDCX)
|
|
Store(1,\_SB.PC00.TRP4.HPSX)
|
|
|
|
//
|
|
// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
|
|
// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
|
|
// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
|
|
// disabled on empty slots prior booting to OS.
|
|
//
|
|
If(LNot(\_SB.PC00.TRP4.PDSX)) {
|
|
// The PCI Express slot is empty, so disable L0s on hot unplug
|
|
//
|
|
Store(0,\_SB.PC00.TRP4.L0SE)
|
|
|
|
}
|
|
// Call Handler for Bios assisted enumeration
|
|
// Handler uses syncronization algoritham to enumerate one Root port
|
|
// at a time
|
|
If(LEqual(ITBS, 1))
|
|
{
|
|
\_GPE.ITBT(0x04)
|
|
}
|
|
// Perform proper notification
|
|
// to the OS.
|
|
Notify(\_SB.PC00.TRP4,0)
|
|
}
|
|
Else
|
|
{
|
|
// False event. Clear Hot-Plug Status
|
|
// then exit.
|
|
|
|
Store(1,\_SB.PC00.TRP4.HPSX)
|
|
}
|
|
}
|
|
|
|
// Check iTBT PCIe Root Port 5 for a Hot Plug Event if the Port is
|
|
// enabled.
|
|
|
|
If(LAnd(LNotEqual(\_SB.PC00.TRP5.VDID,0xFFFFFFFF),\_SB.PC00.TRP5.HPSX))
|
|
{
|
|
// Delay for 100ms to meet the timing requirements
|
|
// of the PCI Express Base Specification, Revision
|
|
// 1.0A, Section 6.6 ("...software must wait at
|
|
// least 100ms from the end of reset of one or more
|
|
// device before it is permitted to issue
|
|
// Configuration Requests to those devices").
|
|
|
|
Sleep(100)
|
|
|
|
If(\_SB.PC00.TRP5.PDCX)
|
|
{
|
|
// Clear all status bits first.
|
|
|
|
Store(1,\_SB.PC00.TRP5.PDCX)
|
|
Store(1,\_SB.PC00.TRP5.HPSX)
|
|
|
|
//
|
|
// PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support
|
|
// In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on
|
|
// hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is
|
|
// disabled on empty slots prior booting to OS.
|
|
//
|
|
If(LNot(\_SB.PC00.TRP5.PDSX)) {
|
|
// The PCI Express slot is empty, so disable L0s on hot unplug
|
|
//
|
|
Store(0,\_SB.PC00.TRP5.L0SE)
|
|
|
|
}
|
|
// Call Handler for Bios assisted enumeration
|
|
// Handler uses syncronization algoritham to enumerate one Root port
|
|
// at a time
|
|
If(LEqual(ITBS, 1))
|
|
{
|
|
\_GPE.ITBT(0x05)
|
|
}
|
|
// Perform proper notification
|
|
// to the OS.
|
|
Notify(\_SB.PC00.TRP5,0)
|
|
}
|
|
Else
|
|
{
|
|
// False event. Clear Hot-Plug Status
|
|
// then exit.
|
|
|
|
Store(1,\_SB.PC00.TRP5.HPSX)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// Software GPE caused the event.
|
|
//
|
|
Method(_L62)
|
|
{
|
|
// Clear GPE status bit.
|
|
Store(0,GPEC)
|
|
|
|
///
|
|
/// Handle HWP SCI event
|
|
///
|
|
If (LEqual(\_SB.HWPI, 1)) {
|
|
If (CondRefOf(\_GPE.HLVT)) {
|
|
\_GPE.HLVT()
|
|
}
|
|
///
|
|
/// Clear HWP interrupt status
|
|
///
|
|
Store(0,\_SB.HWPI)
|
|
}
|
|
///
|
|
/// Handle Intel Turbo Boost Max Technology 3.0 SCI event
|
|
///
|
|
If (LEqual(\_SB.ITBI, 1)) {
|
|
If (CondRefOf(\_GPE.ITBH)) {
|
|
\_GPE.ITBH()
|
|
}
|
|
///
|
|
/// Clear interrupt status
|
|
///
|
|
Store(0,\_SB.ITBI)
|
|
}
|
|
}
|
|
|
|
// IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC).
|
|
|
|
Method(_L66)
|
|
{
|
|
If(LAnd(\_SB.PC00.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI event?
|
|
{
|
|
\_SB.PC00.GFX0.GSCI() // Handle the SWSCI
|
|
}
|
|
}
|
|
|
|
}
|