309 lines
26 KiB
C
309 lines
26 KiB
C
/** @file
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2020 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _ALDERLAKE_CONFIG_PATCH_TABLE_H_
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#define _ALDERLAKE_CONFIG_PATCH_TABLE_H_
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#include <Library/SetupInitLib.h>
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#include <SetupVariable.h>
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#include <Protocol/RetimerCapsuleUpdate.h>
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CONFIG_PATCH_TABLE mAlderLakePRvpSetupConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD (SETUP_DATA, PchI2cSensorDevicePort[SERIAL_IO_I2C0]), OFFSET_OF (SETUP_DATA, PchI2cSensorDevicePort[SERIAL_IO_I2C0]), (SERIAL_IO_I2C_TOUCHPAD|SERIAL_IO_I2C_TOUCHPANEL) },
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{ SIZE_OF_FIELD (SETUP_DATA, AuxOriOverrideSupport), OFFSET_OF (SETUP_DATA, AuxOriOverrideSupport), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, DiscreteTbtPlatformConfigurationSupport),OFFSET_OF (SETUP_DATA, DiscreteTbtPlatformConfigurationSupport), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, HebcValueSupport), OFFSET_OF (SETUP_DATA, HebcValueSupport), 1 },
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{ SIZE_OF_FIELD (SETUP_DATA, SensorHubType), OFFSET_OF (SETUP_DATA, SensorHubType), 1 },
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{ SIZE_OF_FIELD (SETUP_DATA, Rp08D3ColdSupport), OFFSET_OF (SETUP_DATA, Rp08D3ColdSupport), 1 }
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};
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CONFIG_PATCH_TABLE mDiscreteThunderboltSetupEnableConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD (SETUP_DATA, DiscreteTbtPlatformConfigurationSupport), OFFSET_OF (SETUP_DATA, DiscreteTbtPlatformConfigurationSupport), 1 }
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};
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CONFIG_PATCH_TABLE mRp08SetupDisableConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD (SETUP_DATA, Rp08D3ColdSupport), OFFSET_OF (SETUP_DATA, Rp08D3ColdSupport), 0 }
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};
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CONFIG_PATCH_TABLE mIntegratedThunderboltSetupDisableConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD (SETUP_DATA, ITbtPcieRootPortSupported[0]), OFFSET_OF (SETUP_DATA, ITbtPcieRootPortSupported[0]), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, ITbtPcieRootPortSupported[1]), OFFSET_OF (SETUP_DATA, ITbtPcieRootPortSupported[1]), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, ITbtPcieRootPortSupported[2]), OFFSET_OF (SETUP_DATA, ITbtPcieRootPortSupported[2]), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, ITbtPcieRootPortSupported[3]), OFFSET_OF (SETUP_DATA, ITbtPcieRootPortSupported[3]), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, ITbtRootPort[0]), OFFSET_OF (SETUP_DATA, ITbtRootPort[0]), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, ITbtRootPort[1]), OFFSET_OF (SETUP_DATA, ITbtRootPort[1]), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, ITbtRootPort[2]), OFFSET_OF (SETUP_DATA, ITbtRootPort[2]), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, ITbtRootPort[3]), OFFSET_OF (SETUP_DATA, ITbtRootPort[3]), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, IntegratedTbtSupport), OFFSET_OF (SETUP_DATA, IntegratedTbtSupport), 0 }
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};
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CONFIG_PATCH_TABLE mIntegratedThunderboltSaSetupDisableConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD(SA_SETUP, TcssItbtPcie0En), OFFSET_OF(SA_SETUP, TcssItbtPcie0En), 0 },
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{ SIZE_OF_FIELD(SA_SETUP, TcssItbtPcie1En), OFFSET_OF(SA_SETUP, TcssItbtPcie1En), 0 },
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{ SIZE_OF_FIELD(SA_SETUP, TcssItbtPcie2En), OFFSET_OF(SA_SETUP, TcssItbtPcie2En), 0 },
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{ SIZE_OF_FIELD(SA_SETUP, TcssItbtPcie3En), OFFSET_OF(SA_SETUP, TcssItbtPcie3En), 0 },
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{ SIZE_OF_FIELD(SA_SETUP, TcssDma0En), OFFSET_OF(SA_SETUP, TcssDma0En), 0 },
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{ SIZE_OF_FIELD(SA_SETUP, TcssDma1En), OFFSET_OF(SA_SETUP, TcssDma1En), 0 }
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};
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// Enable only "AuxOriOverrideSupport" for board which can support Aux Ori Override after some board rework, not by default configuration.
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CONFIG_PATCH_TABLE mAlderLakePAuxOverrideSupportSetupConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD (SETUP_DATA, AuxOriOverrideSupport), OFFSET_OF (SETUP_DATA, AuxOriOverrideSupport), 1 }
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};
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// Enable both "AuxOriOverrideSupport" and "AuxOriOverride" for boards which have atleast one Type-C Port as Retimerless port.
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// Or having Aux Ori Override support by default.
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CONFIG_PATCH_TABLE mAlderLakePAuxOverrideEnableSetupConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD (SETUP_DATA, AuxOriOverrideSupport), OFFSET_OF (SETUP_DATA, AuxOriOverrideSupport), 1 },
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{ SIZE_OF_FIELD (SETUP_DATA, AuxOriOverride), OFFSET_OF (SETUP_DATA, AuxOriOverride), 1 }
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};
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//
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// Disable iTBT PCIE RP and corresponding DMA controller if Type-C PORT is not having Retimer. So No PCIE Support.
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//
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// LP5-T4 board, TCP2 (count starts from 0), this port is USB/DP only port.
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CONFIG_PATCH_TABLE mAlderLakePLp5T4iTBTPcieRpDmaSaSetupDisableConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD(SA_SETUP, TcssItbtPcie2En), OFFSET_OF(SA_SETUP, TcssItbtPcie2En), 0 }
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};
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// LP5-T3 board, TCP1,TCP2 and TCP3 are USB/DP only ports. So here also for all of these 3 ports PCIe RP should be disabled.
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// DMA1 also should be disabled for T3 board as both ports on controller1 are Non-TBT.
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CONFIG_PATCH_TABLE mAlderLakePLp5T3iTBTPcieRpDmaSaSetupDisableConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD(SA_SETUP, TcssItbtPcie1En), OFFSET_OF(SA_SETUP, TcssItbtPcie1En), 0 },
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{ SIZE_OF_FIELD(SA_SETUP, TcssItbtPcie2En), OFFSET_OF(SA_SETUP, TcssItbtPcie2En), 0 },
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{ SIZE_OF_FIELD(SA_SETUP, TcssItbtPcie3En), OFFSET_OF(SA_SETUP, TcssItbtPcie3En), 0 },
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{ SIZE_OF_FIELD(SA_SETUP, TcssDma1En), OFFSET_OF(SA_SETUP, TcssDma1En), 0 }
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};
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// DDR4, TCP3 is Fixed DP only config which doesn't require PCIe RP.
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CONFIG_PATCH_TABLE mAlderLakePDdr4iTBTPcieRpDmaSaSetupDisableConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD(SA_SETUP, TcssItbtPcie3En), OFFSET_OF(SA_SETUP, TcssItbtPcie3En), 0x0 },
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};
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CONFIG_PATCH_TABLE mAlderLakePTcssUcmDisableSetupConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD (SETUP_DATA, TcssUcmDevice), OFFSET_OF (SETUP_DATA, TcssUcmDevice), 0 }
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};
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CONFIG_PATCH_TABLE mAlderLakePDdr4Ddr5SetupConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD (SETUP_DATA, CvfSupport), OFFSET_OF (SETUP_DATA, CvfSupport), 0 }
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};
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CONFIG_PATCH_TABLE mAlderLakePRvpPchSetupConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD(PCH_SETUP, PmcLpmS0i2p1En), OFFSET_OF(PCH_SETUP, PmcLpmS0i2p1En), 0 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchSerialIoSpi[SERIAL_IO_SPI1]), OFFSET_OF(PCH_SETUP, PchSerialIoSpi[SERIAL_IO_SPI1]), 1 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchUartHwFlowCtrl[SERIAL_IO_UART0]), OFFSET_OF(PCH_SETUP, PchUartHwFlowCtrl[SERIAL_IO_UART0]), 0 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchSerialIoI2c[SERIAL_IO_I2C0]), OFFSET_OF(PCH_SETUP, PchSerialIoI2c[SERIAL_IO_I2C0]), 1 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchSerialIoI2c[SERIAL_IO_I2C1]), OFFSET_OF(PCH_SETUP, PchSerialIoI2c[SERIAL_IO_I2C1]), 1 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchSerialIoI2c[SERIAL_IO_I2C2]), OFFSET_OF(PCH_SETUP, PchSerialIoI2c[SERIAL_IO_I2C2]), 0 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchSerialIoI2c[SERIAL_IO_I2C3]), OFFSET_OF(PCH_SETUP, PchSerialIoI2c[SERIAL_IO_I2C3]), 0 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchSerialIoI2c[SERIAL_IO_I2C4]), OFFSET_OF(PCH_SETUP, PchSerialIoI2c[SERIAL_IO_I2C4]), 0 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchSerialIoI2c[SERIAL_IO_I2C5]), OFFSET_OF(PCH_SETUP, PchSerialIoI2c[SERIAL_IO_I2C5]), 1 },
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// PchIshGpEnable[GP_INDEX 7] Needs to be enabled to put GPPC_B_15_TIME_SYNC_0_ISH_GP_7 PadMode to Function 5.
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{ SIZE_OF_FIELD(PCH_SETUP, PchIshGpEnable[7]), OFFSET_OF(PCH_SETUP, PchIshGpEnable[7]), 1 },
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{ SIZE_OF_FIELD(PCH_SETUP, CnviBtAudioOffload), OFFSET_OF(PCH_SETUP, CnviBtAudioOffload), 1 }
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};
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CONFIG_PATCH_TABLE mAlderLakePLp5GcsPchSetupConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD(PCH_SETUP, PchLan), OFFSET_OF(PCH_SETUP, PchLan), 0 },
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{ SIZE_OF_FIELD(PCH_SETUP, ThcPort0Assignment), OFFSET_OF(PCH_SETUP, ThcPort0Assignment), 1 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchHdAudioHdaLinkEnable), OFFSET_OF(PCH_SETUP, PchHdAudioHdaLinkEnable), 0 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchHdAudioSndwLinkEnable[0]), OFFSET_OF(PCH_SETUP, PchHdAudioSndwLinkEnable[0]), 1 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchHdAudioSndwLinkEnable[1]), OFFSET_OF(PCH_SETUP, PchHdAudioSndwLinkEnable[1]), 1 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchHdAudioSndwLinkEnable[2]), OFFSET_OF(PCH_SETUP, PchHdAudioSndwLinkEnable[2]), 1 }
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};
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CONFIG_PATCH_TABLE mAlderLakePLp5GcsSetupConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD (SETUP_DATA, Rtd3Support), OFFSET_OF (SETUP_DATA, Rtd3Support), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, PowermeterDeviceEnable), OFFSET_OF (SETUP_DATA, PowermeterDeviceEnable), 1 },
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{ SIZE_OF_FIELD (SETUP_DATA, CvfSupport), OFFSET_OF (SETUP_DATA, CvfSupport), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, PchI2cTouchPadType), OFFSET_OF (SETUP_DATA, PchI2cTouchPadType), 7 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_ControlLogic0), OFFSET_OF (SETUP_DATA, MipiCam_ControlLogic0), 1 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_ControlLogic1), OFFSET_OF (SETUP_DATA, MipiCam_ControlLogic1), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_ControlLogic2), OFFSET_OF (SETUP_DATA, MipiCam_ControlLogic2), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_ControlLogic3), OFFSET_OF (SETUP_DATA, MipiCam_ControlLogic3), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_Link0), OFFSET_OF (SETUP_DATA, MipiCam_Link0), 1 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_Link1), OFFSET_OF (SETUP_DATA, MipiCam_Link1), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_Link1_FlashDriverSelection), OFFSET_OF (SETUP_DATA, MipiCam_Link1_FlashDriverSelection), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_Link2), OFFSET_OF (SETUP_DATA, MipiCam_Link2), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_Link3), OFFSET_OF (SETUP_DATA, MipiCam_Link3), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_ControlLogic0_Type), OFFSET_OF (SETUP_DATA, MipiCam_ControlLogic0_Type), 2 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_ControlLogic0_CrdVersion), OFFSET_OF (SETUP_DATA, MipiCam_ControlLogic0_CrdVersion), 0x50 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_ControlLogic0_InputClock), OFFSET_OF (SETUP_DATA, MipiCam_ControlLogic0_InputClock), 0x10 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_ControlLogic0_PchClockSource), OFFSET_OF (SETUP_DATA, MipiCam_ControlLogic0_PchClockSource), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_ControlLogic0_Pld), OFFSET_OF (SETUP_DATA, MipiCam_ControlLogic0_Pld), 0x29 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_ControlLogic0_I2cChannel), OFFSET_OF (SETUP_DATA, MipiCam_ControlLogic0_I2cChannel), 1 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_Link0_SensorModel), OFFSET_OF (SETUP_DATA, MipiCam_Link0_SensorModel), 16 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_Link0_LanesClkDiv), OFFSET_OF (SETUP_DATA, MipiCam_Link0_LanesClkDiv), 0x00 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_Link0_DriverData_CrdVersion), OFFSET_OF (SETUP_DATA, MipiCam_Link0_DriverData_CrdVersion), 0x50 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_Link0_DriverData_ControlLogic), OFFSET_OF (SETUP_DATA, MipiCam_Link0_DriverData_ControlLogic), 0 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_Link0_CameraPhysicalLocation), OFFSET_OF (SETUP_DATA, MipiCam_Link0_CameraPhysicalLocation), 0x61 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_Link0_DriverData_FlashSupport), OFFSET_OF (SETUP_DATA, MipiCam_Link0_DriverData_FlashSupport), 3 },
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{ SIZE_OF_FIELD (SETUP_DATA, MipiCam_Link0_DriverData_PmicPosition), OFFSET_OF (SETUP_DATA, MipiCam_Link0_DriverData_PmicPosition), 1 },
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{ SIZE_OF_FIELD(SETUP_DATA, MipiCam_Link0_ModuleName[0]), OFFSET_OF(SETUP_DATA, MipiCam_Link0_ModuleName[0]), 0x35 }, // Set default to 56B6 for ADL-P GCS
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{ SIZE_OF_FIELD(SETUP_DATA, MipiCam_Link0_ModuleName[1]), OFFSET_OF(SETUP_DATA, MipiCam_Link0_ModuleName[1]), 0x36 },
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{ SIZE_OF_FIELD(SETUP_DATA, MipiCam_Link0_ModuleName[2]), OFFSET_OF(SETUP_DATA, MipiCam_Link0_ModuleName[2]), 0x42 },
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{ SIZE_OF_FIELD(SETUP_DATA, MipiCam_Link0_ModuleName[3]), OFFSET_OF(SETUP_DATA, MipiCam_Link0_ModuleName[3]), 0x36 },
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{ SIZE_OF_FIELD(SETUP_DATA, MipiCam_Link0_DriverData_LinkUsed), OFFSET_OF(SETUP_DATA, MipiCam_Link0_DriverData_LinkUsed), 1 },
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{ SIZE_OF_FIELD(SETUP_DATA, MipiCam_Link0_DriverData_LaneUsed), OFFSET_OF(SETUP_DATA, MipiCam_Link0_DriverData_LaneUsed), 1 },
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{ SIZE_OF_FIELD(SETUP_DATA, MipiCam_Link0_DriverData_EepromType), OFFSET_OF(SETUP_DATA, MipiCam_Link0_DriverData_EepromType), 0x00 },
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{ SIZE_OF_FIELD(SETUP_DATA, MipiCam_Link0_DriverData_VcmType), OFFSET_OF(SETUP_DATA, MipiCam_Link0_DriverData_VcmType), 0x00 },
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{ SIZE_OF_FIELD(SETUP_DATA, MipiCam_Link0_I2cDevicesEnabled), OFFSET_OF(SETUP_DATA, MipiCam_Link0_I2cDevicesEnabled), 1 },
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{ SIZE_OF_FIELD(SETUP_DATA, MipiCam_Link0_I2cChannel), OFFSET_OF(SETUP_DATA, MipiCam_Link0_I2cChannel), 1 },
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{ SIZE_OF_FIELD(SETUP_DATA, MipiCam_Link0_I2cAddress[0]), OFFSET_OF(SETUP_DATA, MipiCam_Link0_I2cAddress[0]), 0x37 }
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};
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CONFIG_PATCH_TABLE mAlderLakePRvpSaSetupConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ 0, 0, 0 } // End of Table
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};
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CONFIG_PATCH_TABLE mAlderLakePRvpCpuSetupConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD(CPU_SETUP, TmeEnable), OFFSET_OF(CPU_SETUP, TmeEnable), 0 },
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{ SIZE_OF_FIELD(CPU_SETUP, EnergyEfficientTurbo), OFFSET_OF(CPU_SETUP, EnergyEfficientTurbo), 1 },
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{ SIZE_OF_FIELD(CPU_SETUP, Irms), OFFSET_OF(CPU_SETUP, Irms), 1 }
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};
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CONFIG_PATCH_TABLE mAlderLakePPchSteppingPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD(PCH_SETUP, PchRetToLowCurModeVolTranTime), OFFSET_OF(PCH_SETUP, PchRetToLowCurModeVolTranTime), 0x2B },
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{ SIZE_OF_FIELD(PCH_SETUP, PchRetToHighCurModeVolTranTime), OFFSET_OF(PCH_SETUP, PchRetToHighCurModeVolTranTime), 0x36 },
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{ 0, 0, 0 } // End of Table
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};
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CONFIG_PATCH_STRUCTURE mAlderLakePPchSteppingConfigPatchStruct[] = {
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{ L"PchSetup", &gPchSetupVariableGuid, sizeof(PCH_SETUP), mAlderLakePPchSteppingPatchTable, SIZE_OF_TABLE(mAlderLakePPchSteppingPatchTable, CONFIG_PATCH_TABLE) },
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};
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CONFIG_PATCH_STRUCTURE mAlderLakePRvpConfigPatchStruct[] = {
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{ L"Setup", &gSetupVariableGuid, sizeof(SETUP_DATA), mAlderLakePRvpSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePRvpSetupConfigPatchTable, CONFIG_PATCH_TABLE) },
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{ L"SaSetup", &gSaSetupVariableGuid, sizeof(SA_SETUP), mAlderLakePRvpSaSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePRvpSaSetupConfigPatchTable, CONFIG_PATCH_TABLE) },
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{ L"CpuSetup", &gCpuSetupVariableGuid, sizeof(CPU_SETUP), mAlderLakePRvpCpuSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePRvpCpuSetupConfigPatchTable, CONFIG_PATCH_TABLE) },
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{ L"PchSetup", &gPchSetupVariableGuid, sizeof(PCH_SETUP), mAlderLakePRvpPchSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePRvpPchSetupConfigPatchTable, CONFIG_PATCH_TABLE) },
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{ L"MeSetup", &gMeSetupVariableGuid, sizeof(ME_SETUP), NULL, 0 }
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};
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CONFIG_PATCH_STRUCTURE mAlderLakePLp4HsioAuxOverrideEnableConfigPatchStruct[] = {
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{ L"Setup", &gSetupVariableGuid, sizeof(SETUP_DATA), mAlderLakePAuxOverrideSupportSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePAuxOverrideSupportSetupConfigPatchTable, CONFIG_PATCH_TABLE) },
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};
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CONFIG_PATCH_STRUCTURE mAlderLakePLp5T4AuxOverrideEnableConfigPatchStruct[] = {
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{ L"Setup", &gSetupVariableGuid, sizeof(SETUP_DATA), mAlderLakePAuxOverrideEnableSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePAuxOverrideEnableSetupConfigPatchTable, CONFIG_PATCH_TABLE) },
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{ L"SaSetup", &gSaSetupVariableGuid, sizeof(SA_SETUP), mAlderLakePLp5T4iTBTPcieRpDmaSaSetupDisableConfigPatchTable, SIZE_OF_TABLE(mAlderLakePLp5T4iTBTPcieRpDmaSaSetupDisableConfigPatchTable, CONFIG_PATCH_TABLE) },
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};
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CONFIG_PATCH_STRUCTURE mAlderLakePLp5T3AuxOverrideEnableConfigPatchStruct[] = {
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{ L"Setup", &gSetupVariableGuid, sizeof(SETUP_DATA), mAlderLakePAuxOverrideEnableSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePAuxOverrideEnableSetupConfigPatchTable, CONFIG_PATCH_TABLE) },
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{ L"SaSetup", &gSaSetupVariableGuid, sizeof(SA_SETUP), mAlderLakePLp5T3iTBTPcieRpDmaSaSetupDisableConfigPatchTable, SIZE_OF_TABLE(mAlderLakePLp5T3iTBTPcieRpDmaSaSetupDisableConfigPatchTable, CONFIG_PATCH_TABLE) },
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};
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CONFIG_PATCH_STRUCTURE mAlderLakePDdr4AuxOverrideEnableConfigPatchStruct[] = {
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{ L"Setup", &gSetupVariableGuid, sizeof(SETUP_DATA), mAlderLakePAuxOverrideSupportSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePAuxOverrideSupportSetupConfigPatchTable, CONFIG_PATCH_TABLE) },
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{ L"SaSetup", &gSaSetupVariableGuid, sizeof(SA_SETUP), mAlderLakePDdr4iTBTPcieRpDmaSaSetupDisableConfigPatchTable, SIZE_OF_TABLE(mAlderLakePDdr4iTBTPcieRpDmaSaSetupDisableConfigPatchTable, CONFIG_PATCH_TABLE) },
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};
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CONFIG_PATCH_STRUCTURE mAlderLakePTcssUcmDisableConfigPatchStruct[] = {
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{ L"Setup", &gSetupVariableGuid, sizeof(SETUP_DATA), mAlderLakePTcssUcmDisableSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePTcssUcmDisableSetupConfigPatchTable, CONFIG_PATCH_TABLE) },
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};
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CONFIG_PATCH_STRUCTURE mAlderLakePDdr4Ddr5ConfigPatchStruct[] = {
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{ L"Setup", &gSetupVariableGuid, sizeof(SETUP_DATA), mAlderLakePDdr4Ddr5SetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePDdr4Ddr5SetupConfigPatchTable, CONFIG_PATCH_TABLE) }
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};
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CONFIG_PATCH_STRUCTURE mDiscreteThunderboltSetupEnableConfigPatchStruct[] = {
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{ L"Setup", &gSetupVariableGuid, sizeof(SETUP_DATA), mDiscreteThunderboltSetupEnableConfigPatchTable, SIZE_OF_TABLE(mDiscreteThunderboltSetupEnableConfigPatchTable, CONFIG_PATCH_TABLE) }
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};
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CONFIG_PATCH_STRUCTURE mRp08SetupDisableConfigPatchStruct[] = {
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{ L"Setup", &gSetupVariableGuid, sizeof(SETUP_DATA), mRp08SetupDisableConfigPatchTable, SIZE_OF_TABLE(mRp08SetupDisableConfigPatchTable, CONFIG_PATCH_TABLE) }
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};
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CONFIG_PATCH_STRUCTURE mIntegratedThunderboltSetupDisableConfigPatchStruct[] = {
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{ L"Setup", &gSetupVariableGuid, sizeof(SETUP_DATA), mIntegratedThunderboltSetupDisableConfigPatchTable, SIZE_OF_TABLE(mIntegratedThunderboltSetupDisableConfigPatchTable, CONFIG_PATCH_TABLE) },
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{ L"SaSetup", &gSaSetupVariableGuid, sizeof(SA_SETUP), mIntegratedThunderboltSaSetupDisableConfigPatchTable, SIZE_OF_TABLE(mIntegratedThunderboltSaSetupDisableConfigPatchTable, CONFIG_PATCH_TABLE) },
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};
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CONFIG_PATCH_STRUCTURE mAlderLakePLp5GcsConfigPatchStruct[] = {
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{ L"PchSetup", &gPchSetupVariableGuid, sizeof(PCH_SETUP), mAlderLakePLp5GcsPchSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePLp5GcsPchSetupConfigPatchTable, CONFIG_PATCH_TABLE) },
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{ L"Setup", &gSetupVariableGuid, sizeof(SETUP_DATA), mAlderLakePLp5GcsSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePLp5GcsSetupConfigPatchTable, CONFIG_PATCH_TABLE) },
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};
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CONFIG_PATCH_TABLE mAlderlakePSimicsSaSetupConfigPatchTable[] = {
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//{---------------Type------Size-----------------------------------Offset----------------------------------------------------Data},
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{ SIZE_OF_FIELD(SA_SETUP, VmdEnable), OFFSET_OF(SA_SETUP, VmdEnable), 0x0 },
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{ SIZE_OF_FIELD(SA_SETUP, VmdGlobalMapping), OFFSET_OF(SA_SETUP, VmdGlobalMapping), 0x0 }
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};
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CONFIG_PATCH_STRUCTURE mAlderlakePSimicsConfigPatchStruct[] = {
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{ L"SaSetup", &gSaSetupVariableGuid, sizeof(SA_SETUP), mAlderlakePSimicsSaSetupConfigPatchTable, SIZE_OF_TABLE(mAlderlakePSimicsSaSetupConfigPatchTable, CONFIG_PATCH_TABLE) }
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};
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CONFIG_PATCH_TABLE mAlderLakePAepPchSetupConfigPatchTable[] = {
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{ SIZE_OF_FIELD(PCH_SETUP, PchHdAudioHdaLinkEnable), OFFSET_OF(PCH_SETUP, PchHdAudioHdaLinkEnable), 0 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchHdAudioSndwLinkEnable[0]), OFFSET_OF(PCH_SETUP, PchHdAudioSndwLinkEnable[0]), 1 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchHdAudioSndwLinkEnable[1]), OFFSET_OF(PCH_SETUP, PchHdAudioSndwLinkEnable[1]), 1 },
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{ SIZE_OF_FIELD(PCH_SETUP, PchHdAudioSndwLinkEnable[2]), OFFSET_OF(PCH_SETUP, PchHdAudioSndwLinkEnable[2]), 1 }
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};
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CONFIG_PATCH_STRUCTURE mAlderLakePAepConfigPatchStruct[] = {
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{ L"PchSetup", &gPchSetupVariableGuid, sizeof(PCH_SETUP), mAlderLakePAepPchSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePAepPchSetupConfigPatchTable, CONFIG_PATCH_TABLE) }
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};
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CONFIG_PATCH_TABLE mAlderLakePDgAepSaSetupConfigPatchTable[] = {
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//{-Type------------------Size-------------------------------------------Offset------------------------------------Data-------------},
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{ SIZE_OF_FIELD(SA_SETUP, PrimaryDisplay), OFFSET_OF(SA_SETUP, PrimaryDisplay), 4 }
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};
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CONFIG_PATCH_STRUCTURE mAlderLakePDgAepConfigPatchStruct[] = {
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{ L"SaSetup", &gSaSetupVariableGuid, sizeof(SA_SETUP), mAlderLakePDgAepSaSetupConfigPatchTable, SIZE_OF_TABLE(mAlderLakePDgAepSaSetupConfigPatchTable, CONFIG_PATCH_TABLE) },
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};
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#endif // _ALDERLAKE_CONFIG_PATCH_TABLE_H_
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