240 lines
6.8 KiB
C
240 lines
6.8 KiB
C
/** @file
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Function prototype of BoardConfigLib.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2015 - 2020 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains a 'Sample Driver' and is licensed as such under the terms
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of your license agreement with Intel or your vendor. This file may be modified
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by the user, subject to the additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _BOARD_CONFIG_LIB_H_
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#define _BOARD_CONFIG_LIB_H_
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#include <Library/GpioLib.h>
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#include <Library/SetupInitLib.h>
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#include <HdAudioConfig.h>
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#include <PlatformBoardConfig.h>
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#define SIZE_OF_FIELD(TYPE, Field) (sizeof (((TYPE *)0)->Field))
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#define SIZE_OF_TABLE(TABLE, TYPE) (sizeof (TABLE) / sizeof (TYPE))
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//
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// @todo Define BOARD_CONFIG
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//
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#define BOARD_CONFIG PLATFORM_INFO
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#define PRE_MEM 0
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#define POST_MEM 1
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#define EARLY_PRE_MEM 2
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/**
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Procedure to detect current board HW configuration.
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**/
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VOID
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EFIAPI
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GetBoardConfig (
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VOID
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);
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EFI_STATUS
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PatchConfigurationDataInit (
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IN CONFIG_PATCH_STRUCTURE *ConfigPatchStruct,
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IN UINTN ConfigPatchStructSize
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);
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/**
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Count the number of GPIO settings in the Table.
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@param[in] GpioTable The pointer of GPIO config table
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@param[out] GpioCount The number of GPIO config entries
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**/
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VOID
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GetGpioTableSize (
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GPIO_INIT_CONFIG *GpioTable,
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OUT UINT16 *GpioCount
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);
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/**
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Configure GPIO Table setting to PcdBoardGpioTablePreMem && PcdBoardGpioTable
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@param[in] GpioTable The pointer of GPIO config table
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@param[in] IsPostMem Is call from PostMem/PreMem
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True - PostMem, False - PreMem
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**/
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VOID
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ConfigureGpioTabletoPCD(
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IN GPIO_INIT_CONFIG *GpioTable,
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IN UINT16 IsPostMem
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);
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/**
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Configure GPIO pads in PEI phase.
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@param[in] GpioTable Pointer to Gpio table
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**/
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VOID
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GpioInit (
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IN GPIO_INIT_CONFIG *GpioTable
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);
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/**
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Configure GPIO group GPE tier.
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**/
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VOID
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GpioGroupTierInit (
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VOID
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);
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/**
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Update board configure patch table.
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@param[in, out] TargetPatchTable Target patch table you want to be updated.
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@param[in, out] TargetPatchTableSize Target patch table size that you want to be updated.
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@param[in] SourcePatchTable Source patch table.
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@param[in] SourcePatchTableSize Source patch table size.
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**/
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VOID
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UpdatePatchTable (
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IN OUT CONFIG_PATCH_STRUCTURE **TargetPatchTable,
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IN OUT UINTN *TargetPatchTableSize,
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IN CONFIG_PATCH_STRUCTURE *SourcePatchTable,
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IN UINTN SourcePatchTableSize
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);
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/**
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Free unused patch table.
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@param[in, out] PatchTable Patch table you want to free memory.
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@param[in, out] PatchTableSize Patch table size that you want to free memory.
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**/
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VOID
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FreePatchTable (
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IN OUT CONFIG_PATCH_STRUCTURE **PatchTable,
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IN OUT UINTN *PatchTableSize
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);
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/**
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Check if given rootport has device connected and enable wake capability
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@param[in] RpNum An unsigned integer represent the root port number.
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@retval TRUE if endpoint was connected
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@retval FALSE if no endpoint was detected
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**/
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BOOLEAN
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IsPcieEndPointPresent (
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IN UINT8 RpNum
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);
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extern HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio;
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extern HDAUDIO_VERB_TABLE HdaVerbTableAlc286S;
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extern HDAUDIO_VERB_TABLE HdaVerbTableAlc298;
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extern HDAUDIO_VERB_TABLE HdaVerbTableAlc700;
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extern HDAUDIO_VERB_TABLE HdaVerbTableAlc701;
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extern HDAUDIO_VERB_TABLE HdaVerbTableAlc274;
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extern HDAUDIO_VERB_TABLE HdaVerbTableAlc711;
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extern HDAUDIO_VERB_TABLE HdaVerbTableCS4207;
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// LPDDR4 200b 8Gb die, DDP, 2 channels per die, x16
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// Samsung K4F6E304Hx-MGCJ
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// or Hynix H9HCNNNBUUxLHR-NMx
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// or Micron MT53B512M32D2NP-053
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// 3733, 32-34-34-79
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// 2 ranks per channel, 2 SDRAMs per channel, 2x2x8Gb = 4GB total per channel
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extern const UINT8 mLpddr4Ddp8Gb200bSpd;
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// LPDDR4X 432b 16Gb die, QDP 2x16
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// Samsung K3UH7H70MM-JGCJ
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// 3733, 32-34-34-79
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// 2 ranks per channel, 1 SDRAMs per rank, 4x16Gb = 8GB total per channel
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extern const UINT8 mLpddr4xQdp16Gb432bSpd;
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// LPDDR4X 556b 8Gb die, ODP, 1 channel per die, x16
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// Micron MT53D1G64D8SQ-046
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// 4266
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// 2 ranks per channel, 2 SDRAMs per channel, 2x4x8Gb = 8GB total per channel
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extern const UINT8 mLpddr4xOdp8Gb556bSpd;
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// LPDDR4X 556b 4Gb die, QDP, 1 channel per die, x16
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// Micron MT53D512M64D4RQ-046 WT:E
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// 4266
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// 2 ranks per channel, 2 SDRAMs per channel, 2x4x8Gb = 4GB total per channel
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extern const UINT8 mLpddr4xQdp4Gb556bSpd;
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extern const UINT8 mLpddr4Ddp16Gb200b1rSpd;
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// LPDDR5 496b 12Gb die, QDP 1x16
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// Samsung K3LK2K20BM-BGCN
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// 5500, ??-??-??-??
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// 16 Banks, 4 bank groups, 12Gb SDRAM density
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// 16 Row bits, 10 Column bits
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// Non-Monolithic DRAM Device, 4 dies, 4 Channels per die,
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extern const UINT8 mLpddr5xQdp12Gb496bSpd;
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// LPDDR4X 200b 16Gb die, DDP, 2 channel per die, 2x8
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// Samsung K4U6E3S4AA-MGCL
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// 4267, 36-39-39-90
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// 1 rank per channel, 2 SDRAMs per channel, 2x8GB = 16GB total per channel
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extern const UINT8 mLpddr4xDdp16Gb200bSpd;
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// LPDDR4X 200b 16Gb die, 2 channel per die, 2x8
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// Micron MT53E1G32D4NQ-046
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// 3200
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extern const UINT8 mLpddr4xQdp16Gb200bSpd;
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// LPDDR4X 200b 8Gb die, 4 die, 2 Channels per package
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// Micron MT53E1G32D4NQ-046
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// 4267
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extern const UINT8 mLpddr4xQdp8Gb200b2r4267Spd;
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extern const UINT8 mDdr5Spd_1Rx8[];
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extern const UINT8 mDdr5Spd_2Rx8[];
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extern USB2_PHY_TABLE mUsb2PhyTuningTable;
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// Default USB2 OC mapping
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extern USB_OC_MAP_TABLE mUsb2OverCurrentMappingTable;
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// Default USB3 OC mapping
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extern USB_OC_MAP_TABLE mUsb3OverCurrentMappingTable;
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/**
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Update Cpu Xhci Port Enable Map PCD from SaSetup data.
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**/
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VOID
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EFIAPI
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TcssUpdateCpuXhciPortEnableMapPcd (
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VOID
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);
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#endif // _BOARD_CONFIG_LIB_H_
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