100 lines
7.1 KiB
Plaintext
100 lines
7.1 KiB
Plaintext
## @file
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# AlderLake S RVP GPIO definition table for Pre-Memory Initialization
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#
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# @copyright
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# INTEL CONFIDENTIAL
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# Copyright 2020 - 2021 Intel Corporation.
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#
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# The source code contained or described herein and all documents related to the
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# source code ("Material") are owned by Intel Corporation or its suppliers or
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# licensors. Title to the Material remains with Intel Corporation or its suppliers
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# and licensors. The Material may contain trade secrets and proprietary and
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# confidential information of Intel Corporation and its suppliers and licensors,
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# and is protected by worldwide copyright and trade secret laws and treaty
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# provisions. No part of the Material may be used, copied, reproduced, modified,
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# published, uploaded, posted, transmitted, distributed, or disclosed in any way
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# without Intel's prior express written permission.
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#
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# No license under any patent, copyright, trade secret or other intellectual
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# property right is granted to or conferred upon you by disclosure or delivery
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# of the Materials, either expressly, by implication, inducement, estoppel or
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# otherwise. Any license under such intellectual property rights must be
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# express and approved by Intel in writing.
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#
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# Unless otherwise agreed by Intel in writing, you may not remove or alter
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# this notice or any other notice embedded in Materials by Intel or
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# Intel's suppliers or licensors in any way.
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#
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# This file contains a 'Sample Driver' and is licensed as such under the terms
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# of your license agreement with Intel or your vendor. This file may be modified
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# by the user, subject to the additional terms of the license agreement.
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#
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# @par Specification
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##
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###
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### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
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### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
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###
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###
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# mGpioTablePreMemAdlSDdr4UDimm2DCrb
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr4UDimm2DCrb]
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gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
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{ GPIO_VER4_S_GPP_E2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, // PEG_1 RTD3 Reset
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{ GPIO_VER4_S_GPP_E3, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, // PEG_2 RTD3 Reset Sinai DR0 (Rework)
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{ GPIO_VER4_S_GPP_F11, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, // PCIe SLOT_1 RTD3 Reset MIPI60 (Rework)
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{ GPIO_VER4_S_GPP_F12, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, // PCIe SLOT_2 RTD3 Reset MIPI60 (Rework)
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{ GPIO_VER4_S_GPP_F13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, // PCIe SLOT_3 RTD3 Reset MIPI60 (Rework)
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{ 0x0 } // terminator
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})}
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# mGpioTablePreMemAdlSDdr5UDimm1DCrb
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr5UDimm1DCrb]
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gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
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{GPIO_VER4_S_GPP_E2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}},//CPU PEG Slot1 Reset
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{GPIO_VER4_S_GPP_F11, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}},//PCIE SLOT 1 - X4 CONNECTOR Reset
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{GPIO_VER4_S_GPP_F12, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermNone}},//PCIE SLOT 2 - X4 CONNECTOR Reset
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{GPIO_VER4_S_GPP_F13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}},//PCIE SLOT 3 - X2 CONNECTOR Reset
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{0x0} // terminator
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})}
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# mGpioTablePreMemAdlSDdr5UDimm1DAep
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSDdr5UDimm1DAep]
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gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
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{GPIO_VER4_S_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }},// PEG SLOT RST_N
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{GPIO_VER4_S_GPP_K4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioResetDefault, GpioTermNone }},// Maple Ridge 1 (Back Panel) TBT_BP_RST_N
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{GPIO_VER4_S_GPP_K3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioResetDefault, GpioTermNone }},// Maple Ridge 2 (Front Panel) TBT_FP_RST_N
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{0x0} // terminator
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})}
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# mGpioTablePreMemmAdlSSbgaDdr5SODimmErb
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSSbgaDdr5SODimmErb]
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gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
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{GPIO_VER4_S_GPP_E2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}},//CPU PEG Slot Reset
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{GPIO_VER4_S_GPP_E17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}},//PCIE SLOT x4 Reset
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{GPIO_VER4_S_GPP_F18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}},//M.2 CPU SSD reset
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{GPIO_VER4_S_GPP_C10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}},//PCH SSD Reset
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{0x0} // terminator
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})}
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# mGpioTablePreMemmAdlSSbgaDdr4SODimmCrb
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSSbgaDdr4SODimmCrb]
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gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
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{GPIO_VER4_S_GPP_E2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, // CPU PEG Slot Reset
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{GPIO_VER4_S_GPP_F22, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, // PCIESLOT_1_RST_N
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{GPIO_VER4_S_GPP_C10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, // PCH SSD Reset
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{GPIO_VER4_S_GPP_F11, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, // CPU SSD reset
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{0x0} // terminator
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})}
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# mGpioTablePreMemAdlSAdpSSbgaDdr5SODimmAep
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[PcdsDynamicExVpd.common.SkuIdAdlSAdpSSbgaDdr5SODimmAep]
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gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
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{GPIO_VER4_S_GPP_E2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}},//CPU PEG Slot Reset
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{GPIO_VER4_S_GPP_F18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}},//PCH SSD1 reset
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{GPIO_VER4_S_GPP_C10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone}},//PCH SSD2 Reset
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{0x0} // terminator
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})}
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