128 lines
9.6 KiB
Plaintext
128 lines
9.6 KiB
Plaintext
## @file
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# GPIO definition table for AlderLake Simics
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#
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# @copyright
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# INTEL CONFIDENTIAL
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# Copyright 2020 Intel Corporation.
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#
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# The source code contained or described herein and all documents related to the
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# source code ("Material") are owned by Intel Corporation or its suppliers or
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# licensors. Title to the Material remains with Intel Corporation or its suppliers
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# and licensors. The Material may contain trade secrets and proprietary and
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# confidential information of Intel Corporation and its suppliers and licensors,
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# and is protected by worldwide copyright and trade secret laws and treaty
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# provisions. No part of the Material may be used, copied, reproduced, modified,
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# published, uploaded, posted, transmitted, distributed, or disclosed in any way
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# without Intel's prior express written permission.
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#
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# No license under any patent, copyright, trade secret or other intellectual
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# property right is granted to or conferred upon you by disclosure or delivery
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# of the Materials, either expressly, by implication, inducement, estoppel or
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# otherwise. Any license under such intellectual property rights must be
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# express and approved by Intel in writing.
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#
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# Unless otherwise agreed by Intel in writing, you may not remove or alter
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# this notice or any other notice embedded in Materials by Intel or
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# Intel's suppliers or licensors in any way.
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#
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# This file contains a 'Sample Driver' and is licensed as such under the terms
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# of your license agreement with Intel or your vendor. This file may be modified
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# by the user, subject to the additional terms of the license agreement.
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#
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# @par Specification
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##
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###
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### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
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### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
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###
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###
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# mGpioTableAdlPDdr4Simics
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[PcdsDynamicExVpd.common.SkuIdAdlPSimics]
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gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|*|{CODE({
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// CPU M.2 SSD
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{GPIO_VER2_LP_GPP_D16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD PWREN
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{GPIO_VER2_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD RESET
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// M.2 Key-E - WLAN/BT
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{GPIO_VER2_LP_GPP_A13, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, // BT_RF_KILL_N
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{GPIO_VER2_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, // WIFI_RF_KILL_N
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{GPIO_VER2_LP_GPP_C22, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, // WLAN_RST_N
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{GPIO_VER2_LP_GPP_A10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNone }}, // M.2 BT
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// All SCI GPIO's are not programmed due to HFPGA issue : 1505908653
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// {GPIO_VER2_LP_GPP_C23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //WIFI_WAKE_N
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// {GPIO_VER2_LP_GPP_H19, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //UART_BT_WAKE_N : Not default POR
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// X4 Pcie Slot for Gen3 and Gen 4
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{GPIO_VER2_LP_GPP_A14, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //ONBOARD_X4_PCIE_SLOT1_PWREN_N
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{GPIO_VER2_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //ONBOARD_X4_PCIE_SLOT1_RESET_N
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// {GPIO_VER2_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //ONBOARD_X4_PCIE_SLOT1_WAKE_N
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{GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //ONBOARD_X4_PCIE_SLOT1_DGPU_SEL
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{GPIO_VER2_LP_GPP_F21, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault,GpioIntDis,GpioPlatformReset, GpioTermNone}}, //ONBOARD_X4_PCIE_SLOT1_DGPU_PWROK
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// TBT Re-Timers
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// {GPIO_VER2_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //TC_RETIMER_FORCE_PWR
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{GPIO_VER2_LP_GPD7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioDswReset, GpioTermNone}}, //TCP_RETIMER_PERST_N
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// Battery Charger Vmin to PCH PROCHOT, derived from TGL
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// {GPIO_VER2_LP_GPP_B2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntEdge|GpioIntSci,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //BC_PROCHOT_N
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// SATA Direct Connect
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{GPIO_VER2_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //SATA_DIRECT_PWREN
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// FPS
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{GPIO_VER2_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //FPS_RST_N
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{GPIO_VER2_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,GpioIntLevel|GpioIntApic,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //FPS_INT
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// PCH M.2 SSD
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{GPIO_VER2_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_PCH_SSD_PWREN
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{GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_SSD_RST_N
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// Camera
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{GPIO_VER2_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CRD_CAM_PWREN - CAM1
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{GPIO_VER2_LP_GPP_C15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WF_CAM_RST_N - CAM1
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{GPIO_VER2_LP_GPP_R6, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CAM2_PWREN/BIOS_REC
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{GPIO_VER2_LP_GPP_H12, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CAM2_RST_N
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{GPIO_VER2_LP_GPP_H15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CAM3_PWREN
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{GPIO_VER2_LP_GPP_H13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CAM3_RST_N
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// Camera Common GPIO's for all Camera, Rework Options
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{GPIO_VER2_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CRD_CAM_STROBE_1
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{GPIO_VER2_LP_GPP_R5, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CRD_CAM_PRIVACY_LED_1
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{GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WF_CAM_CLK_EN
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// Audio
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{GPIO_VER2_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //SPKR_PD_N
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{GPIO_VER2_LP_GPP_C12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntApic,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, // CODEC_INT_N
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// Touch Pad
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// Touch Pad and Touch Panel 2 share the same Power Enable, default is Touch pad
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{GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //TCH_PAD_LS_EN - PWR_En
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{GPIO_VER2_LP_GPP_C8, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault,GpioIntEdge|GpioIntApic,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //TCH_PAD_INT_N
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// EC
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// {GPIO_VER2_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //EC_SMI_N
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{GPIO_VER2_LP_GPP_E8, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //EC_SLP_S0_CS_N
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// SPI TPM, derived from TGL
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// {GPIO_VER2_LP_GPP_C14, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //SPI_TPM_INT_N
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// TypeC BIAS : Not used by default in RVP, derived from TGL
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{GPIO_VER2_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //DISP_AUX_P_BIAS_GPIO
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{GPIO_VER2_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //DISP_AUX_N_BIAS_GPIO
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// LAN : Not used by Default in RVP
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{GPIO_VER2_LP_GPP_F7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //LAN_RST_N
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// X1 Pcie Slot
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{GPIO_VER2_LP_GPP_F9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //X1 Slot PWREN
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{GPIO_VER2_LP_GPP_F4, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //X1 Slot WAKE
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{GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //X1 Slot RESET
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{0x0} // terminator
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})}
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