53 lines
3.1 KiB
Plaintext
53 lines
3.1 KiB
Plaintext
## @file
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# Alderlake Simics RVP GPIO definition table for Pre-Memory Initialization
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#
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# @copyright
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# INTEL CONFIDENTIAL
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# Copyright 2020 Intel Corporation.
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#
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# The source code contained or described herein and all documents related to the
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# source code ("Material") are owned by Intel Corporation or its suppliers or
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# licensors. Title to the Material remains with Intel Corporation or its suppliers
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# and licensors. The Material may contain trade secrets and proprietary and
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# confidential information of Intel Corporation and its suppliers and licensors,
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# and is protected by worldwide copyright and trade secret laws and treaty
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# provisions. No part of the Material may be used, copied, reproduced, modified,
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# published, uploaded, posted, transmitted, distributed, or disclosed in any way
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# without Intel's prior express written permission.
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#
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# No license under any patent, copyright, trade secret or other intellectual
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# property right is granted to or conferred upon you by disclosure or delivery
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# of the Materials, either expressly, by implication, inducement, estoppel or
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# otherwise. Any license under such intellectual property rights must be
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# express and approved by Intel in writing.
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#
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# Unless otherwise agreed by Intel in writing, you may not remove or alter
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# this notice or any other notice embedded in Materials by Intel or
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# Intel's suppliers or licensors in any way.
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#
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# This file contains a 'Sample Driver' and is licensed as such under the terms
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# of your license agreement with Intel or your vendor. This file may be modified
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# by the user, subject to the additional terms of the license agreement.
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#
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# @par Specification
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##
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###
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### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
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### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
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###
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###
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# mGpioTablePreMemAdlPDdr4Simics
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[PcdsDynamicExVpd.common.SkuIdAdlPSimics]
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gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
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{GPIO_VER2_LP_GPP_C11, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WWAN_FCP_OFF_N
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{GPIO_VER2_LP_GPP_D15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WWAN_DISABLE_N
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{GPIO_VER2_LP_GPP_H23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WWAN_PWREN
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{GPIO_VER2_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WWAN_PERST_N
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// {GPIO_VER2_LP_GPP_C9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //WWAN_WAKE_N
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{GPIO_VER2_LP_GPP_C10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WWAN_RST_N
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{GPIO_VER2_LP_GPP_A23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //TC_RETIMER_FORCE_PWR
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{0x0} // terminator
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})}
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