109 lines
4.6 KiB
Plaintext
109 lines
4.6 KiB
Plaintext
## @file
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# ADL M DQ configuration file.
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#
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# @copyright
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# INTEL CONFIDENTIAL
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# Copyright 2021 Intel Corporation.
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#
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# The source code contained or described herein and all documents related to the
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# source code ("Material") are owned by Intel Corporation or its suppliers or
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# licensors. Title to the Material remains with Intel Corporation or its suppliers
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# and licensors. The Material may contain trade secrets and proprietary and
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# confidential information of Intel Corporation and its suppliers and licensors,
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# and is protected by worldwide copyright and trade secret laws and treaty
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# provisions. No part of the Material may be used, copied, reproduced, modified,
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# published, uploaded, posted, transmitted, distributed, or disclosed in any way
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# without Intel's prior express written permission.
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#
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# No license under any patent, copyright, trade secret or other intellectual
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# property right is granted to or conferred upon you by disclosure or delivery
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# of the Materials, either expressly, by implication, inducement, estoppel or
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# otherwise. Any license under such intellectual property rights must be
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# express and approved by Intel in writing.
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#
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# Unless otherwise agreed by Intel in writing, you may not remove or alter
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# this notice or any other notice embedded in Materials by Intel or
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# Intel's suppliers or licensors in any way.
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#
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# This file contains a 'Sample Driver' and is licensed as such under the terms
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# of your license agreement with Intel or your vendor. This file may be modified
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# by the user, subject to the additional terms of the license agreement.
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#
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# @par Specification
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##
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[PcdsDynamicExVpd.common.SkuIdAdlMLp4Rvp]
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gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram|*|{CODE({{
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//
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// ADL-M LPDDR4 RVP DQ bit swizzling between CPU and DRAM
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//
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//Controller 0
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{{ 11, 15, 10, 9, 8, 14, 13, 12 }, // Byte 0
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{ 0, 5, 4, 1, 6, 7, 2, 3 }}, // Byte 1
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{{ 11, 15, 10, 9, 12, 8, 14, 13 }, // Byte 2
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{ 0, 1, 5, 4, 7, 6, 2, 3 }}, // Byte 3
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{{ 3, 2, 7, 6, 1, 0, 4, 5 }, // Byte 4
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{ 12, 14, 8, 13, 9, 15, 10, 11 }}, // Byte 5
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{{ 7, 6, 2, 3, 1, 5, 0, 4 }, // Byte 6
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{ 8, 12, 14, 13, 15, 10, 11, 9 }}, // Byte 7
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//Controller 1
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{{ 11, 9, 15, 10, 12, 8, 14, 13 }, // Byte 0
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{ 0, 5, 4, 1, 6, 7, 2, 3 }}, // Byte 1
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{{ 15, 11, 9, 10, 14, 12, 13, 8 }, // Byte 2
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{ 0, 1, 5, 4, 6, 7, 3, 2 }}, // Byte 3
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{{ 2, 7, 6, 3, 4, 1, 5, 0 }, // Byte 4
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{ 12, 13, 8, 14, 9, 10, 15, 11 }}, // Byte 5
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{{ 7, 3, 6, 2, 5, 4, 0, 1 }, // Byte 6
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{ 13, 14, 8, 12, 11, 9, 10, 15 }} // Byte 7
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}})}
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[PcdsDynamicExVpd.common.SkuIdAdlMLp5Rvp]
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gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram|*|{CODE({{
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//
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// ADL-M LPDDR5 RVP2/RVP3 DQ bit swizzling between CPU and DRAM
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//
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//Controller 0
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{{ 1, 0, 2, 3, 4, 7, 6, 5 }, // Byte 0
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{ 13, 14, 9, 11, 12, 15, 10, 8 }}, // Byte 1
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{{ 1, 0, 2, 3, 7, 4, 5, 6 }, // Byte 2
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{ 14, 15, 13, 12, 8, 10, 11, 9 }}, // Byte 3
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{{ 0, 2, 7, 4, 1, 6, 3, 5 }, // Byte 4
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{ 13, 15, 12, 14, 11, 8, 10, 9 }}, // Byte 5
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{{ 0, 2, 3, 1, 7, 5, 6, 4 }, // Byte 6
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{ 12, 15, 13, 14, 8, 10, 9, 11 }}, // Byte 7
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//Controller 1
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{{ 1, 3, 0, 2, 5, 4, 7, 6 }, // Byte 0
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{ 13, 14, 9, 11, 12, 15, 10, 8 }}, // Byte 1
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{{ 0, 1, 3, 2, 5, 7, 6, 4 }, // Byte 2
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{ 14, 15, 13, 12, 10, 8, 9, 11 }}, // Byte 3
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{{ 2, 7, 4, 0, 1, 3, 6, 5 }, // Byte 4
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{ 13, 15, 12, 14, 11, 10, 8, 9 }}, // Byte 5
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{{ 0, 1, 2, 3, 5, 4, 6, 7 }, // Byte 6
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{ 14, 13, 12, 15, 9, 11, 10, 8 }} // Byte 7
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}})}
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[PcdsDynamicExVpd.common.SkuIdAdlMLp5Aep]
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gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram|*|{CODE({{
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//
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// ADL-M LPDDR5 AEP DQ bit swizzling between CPU and DRAM
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//
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//Controller 0
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{{ 3, 1, 0, 5, 4, 2, 7, 6 }, // Byte 0
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{ 14, 13, 9, 11, 8, 12, 10, 15 }}, // Byte 1
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{{ 3, 0, 1, 2, 5, 4, 7, 6 }, // Byte 2
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{ 13, 12, 14, 9, 15, 2, 11, 8 }}, // Byte 3
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{{ 7, 2, 4, 0, 1, 6, 3, 5 }, // Byte 4
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{ 13, 14, 12, 15, 10, 9, 11, 8 }}, // Byte 5
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{{ 7, 2, 3, 0, 4, 6, 5, 1 }, // Byte 6
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{ 12, 13, 14, 15, 8, 10, 9, 11 }}, // Byte 7
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//Controller 1
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{{ 0, 2, 1, 3, 5, 4, 7, 6 }, // Byte 0
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{ 13, 11, 14, 9, 12, 15, 8, 10 }}, // Byte 1
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{{ 1, 0, 2, 3, 7, 5, 6, 4 }, // Byte 2
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{ 14, 12, 13, 9, 10, 15, 0, 11 }}, // Byte 3
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{{ 2, 4, 0, 7, 1, 3, 6, 5 }, // Byte 4
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{ 13, 14, 12, 15, 10, 11, 9, 8 }}, // Byte 5
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{{ 2, 3, 7, 0, 4, 1, 5, 6 }, // Byte 6
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{ 15, 14, 12, 13, 9, 10, 11, 8 }} // Byte 7
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}})}
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