1530 lines
100 KiB
Plaintext
1530 lines
100 KiB
Plaintext
## @file
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# Chipset Package Declaration file
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#
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#******************************************************************************
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#* Copyright (c) 2014 - 2021, Insyde Software Corp. All Rights Reserved.
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#*
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#* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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#* transmit, broadcast, present, recite, release, license or otherwise exploit
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#* any part of this publication in any form, by any means, without the prior
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#* written permission of Insyde Software Corporation.
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#*
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#******************************************************************************
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##
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[Defines]
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DEC_SPECIFICATION = 0x00010005
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PACKAGE_NAME = AlderLakeChipsetPkg
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PACKAGE_GUID = DF131C26-D59D-45c8-A8EB-2BFD518D8BA9
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PACKAGE_VERSION = 0.1
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[Includes]
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Include
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Override/Insyde/InsydeModulePkg/Include
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Include/Library/sventx
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Override/EDK2/FmpDevicePkg/PrivateInclude
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#
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# SetupUtility
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#
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UefiSetupUtilityDxe/Advance
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[LibraryClasses]
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SecOemSvcChipsetLibDefault|Include/Library/SecOemSvcChipsetLib.h
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PeiOemSvcChipsetLibDefault|Include/Library/PeiOemSvcChipsetLib.h
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DxeOemSvcChipsetLibDefault|Include/Library/DxeOemSvcChipsetLib.h
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SmmOemSvcChipsetLibDefault|Include/Library/SmmOemSvcChipsetLib.h
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BaseOemSvcChipsetLibDefault|Include/Library/BaseOemSvcChipsetLib.h
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BootGuardPlatformLib|Include/Library/BootGuardPlatformLib.h
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FitPlatformLib|Include/Library/FitPlatformLib.h
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BaseInsydeChipsetLib|Include/Library/BaseInsydeChipsetLib.h
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DxeInsydeChipsetLib|Include/Library/DxeInsydeChipsetLib.h
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PeiInsydeChipsetLib|Include/Library/PeiInsydeChipsetLib.h
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GpioCfgLib|Include/Library/GpioCfgLib.h
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InsydeChipsetGpioLib|Include/Library/BaseInsydeChipsetGpioLib.h
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MultiBoardSupportLib|Include/Library/MultiBoardSupportLib.h
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[PcdsFeatureFlag]
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#
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# Hybrid Graphics Support
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#
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gChipsetPkgTokenSpaceGuid.PcdHybridGraphicsSupported|FALSE|BOOLEAN|0x56000001
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gChipsetPkgTokenSpaceGuid.PcdNvidiaOptimusSupported|FALSE|BOOLEAN|0x56000002
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gChipsetPkgTokenSpaceGuid.PcdAmdPowerXpressSupported|FALSE|BOOLEAN|0x56000003
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gChipsetPkgTokenSpaceGuid.PcdHgAslCodeForWptLynxPointLp|FALSE|BOOLEAN|0x56000004
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## Indicates if the platform can support Dynamic Display Switching (DDS) or not.
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# TRUE - Supports DDS.
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# FALSE - Not supports DDS.
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# @Prompt Enalbe DDS support.
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gChipsetPkgTokenSpaceGuid.PcdHgNvidiaDdsFeatureSupport|FALSE|BOOLEAN|0x56000005
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## Indicates if the platform can support N20 CTGP or not.
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# TRUE - Supports N20 CTGP.
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# FALSE - Not supports N20 CTGP.
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# @Prompt Enable N20 CTGP support.
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gChipsetPkgTokenSpaceGuid.PcdHgNvidiaCtgpFeatureSupport|FALSE|BOOLEAN|0x56000006
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## Indicates if the platform can support N20 API_CPU_PERFORMANCE_LEVEL_CONTROL or not.
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# TRUE - Supports N20 API_CPU_PERFORMANCE_LEVEL_CONTROL.
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# FALSE - Not supports N20 API_CPU_PERFORMANCE_LEVEL_CONTROL.
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# @Prompt Enable N20 API_CPU_PERFORMANCE_LEVEL_CONTROL.
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gChipsetPkgTokenSpaceGuid.PcdHgNvidiaApiCpuPerformanceLevelControl|FALSE|BOOLEAN|0x56000007
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gChipsetPkgTokenSpaceGuid.PcdEcSharedFlashSupported|FALSE|BOOLEAN|0x1000000A
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gChipsetPkgTokenSpaceGuid.PcdEcIdlePerWriteBlockSupported|FALSE|BOOLEAN|0x1000000B
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gChipsetPkgTokenSpaceGuid.PcdMemSpdProtectionSupported|FALSE|BOOLEAN|0x40000002
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gChipsetPkgTokenSpaceGuid.PcdTXTSupported|FALSE|BOOLEAN|0x40000005
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gChipsetPkgTokenSpaceGuid.PcdSmmInt10Enable|FALSE|BOOLEAN|0x40000017
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gChipsetPkgTokenSpaceGuid.PcdBiosGuardEcSupport|FALSE|BOOLEAN|0x40000023
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#
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# Determine the SPI access method (1: MMIO / 0: IO Cycle)
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#
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gChipsetPkgTokenSpaceGuid.PcdSpiReadByMemoryMapped|TRUE|BOOLEAN|0x40000024
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#
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# The PcdDisableCacheSupportInEnableFdWrites is used for EnableFdWrites function ,support to enable/disable cache function when doing the FdWrite
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# TRUE: Support DisableCache function , FALSE: No Support DisableCache function
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gChipsetPkgTokenSpaceGuid.PcdDisableCacheSupportInEnableFdWrites|TRUE|BOOLEAN|0x40000026
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gChipsetPkgTokenSpaceGuid.PcdPttSupported|FALSE|BOOLEAN|0x40000030
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gChipsetPkgTokenSpaceGuid.PcdUseClockRateAsTheUnitOfConfiguredClockSpeed|FALSE|BOOLEAN|0x40000031
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gChipsetPkgTokenSpaceGuid.PcdUseCrbEcFlag|TRUE|BOOLEAN|0x40000034
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gChipsetPkgTokenSpaceGuid.PcdEnableEconFlag|TRUE|BOOLEAN|0x40000035
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gChipsetPkgTokenSpaceGuid.PcdRestoreCmosfromVariableFlag|FALSE|BOOLEAN|0x40000038
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gChipsetPkgTokenSpaceGuid.PcdMeUnconfigOnRtcSupported|FALSE|BOOLEAN|0x40000039
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## This PCD specifies whether StatusCode is reported via NorthPeak.
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gEfiTraceHubTokenSpaceGuid.PcdStatusCodeUseTraceHub|TRUE|BOOLEAN|0x40000040
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gChipsetPkgTokenSpaceGuid.PcdSupportUnLockedBarHandle|FALSE|BOOLEAN|0x4000003B
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gChipsetPkgTokenSpaceGuid.PcdIhisiToolBackwardSupport|FALSE|BOOLEAN|0x4000003C
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gChipsetPkgTokenSpaceGuid.PcdDisableScuAggressiveLpmSupportForPchH|FALSE|BOOLEAN|0x4000003D
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gChipsetPkgTokenSpaceGuid.PcdSklU6LayerAvoidLLViolationSupport|FALSE|BOOLEAN|0x4000003E
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gChipsetPkgTokenSpaceGuid.PcdDebugUsePchComPort|FALSE|BOOLEAN|0x40000040
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gChipsetPkgTokenSpaceGuid.PcdBootGuardVerifyFv|TRUE|BOOLEAN|0x40000041
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gChipsetPkgTokenSpaceGuid.PcdHstiSupported|FALSE|BOOLEAN|0x40000042
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gChipsetPkgTokenSpaceGuid.PcdSmiNewCenturySupport|TRUE|BOOLEAN|0x40000044
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gChipsetPkgTokenSpaceGuid.PcdH2OIDEGPIOEditor|FALSE|BOOLEAN|0x40000046
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gChipsetPkgTokenSpaceGuid.PcdComPortDdt|FALSE|BOOLEAN|0x40000047
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gChipsetPkgTokenSpaceGuid.PcdMeCapsuleUpdateSupported|TRUE|BOOLEAN|0x40000048
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gChipsetPkgTokenSpaceGuid.PcdIshCapsuleUpdateSupported|TRUE|BOOLEAN|0x40000049
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gChipsetPkgTokenSpaceGuid.PcdH2OGpioCfgSupported|FALSE|BOOLEAN|0x40000052
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gChipsetPkgTokenSpaceGuid.PcdEcCapsuleUpdateSupported|TRUE|BOOLEAN|0x40000053
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gChipsetPkgTokenSpaceGuid.PcdPdtCapsuleUpdateSupported|TRUE|BOOLEAN|0x40000054
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gChipsetPkgTokenSpaceGuid.PcdIomCapsuleUpdateSupported|TRUE|BOOLEAN|0x40000055
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gChipsetPkgTokenSpaceGuid.PcdMgPhyCapsuleUpdateSupported|TRUE|BOOLEAN|0x40000056
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gChipsetPkgTokenSpaceGuid.PcdTbtCapsuleUpdateSupported|TRUE|BOOLEAN|0x40000057
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gChipsetPkgTokenSpaceGuid.PcdUcodeCapsuleUpdateSupported|TRUE|BOOLEAN|0x40000066
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gChipsetPkgTokenSpaceGuid.PcdBtGAcmCapsuleUpdateSupported|TRUE|BOOLEAN|0x40000067
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gChipsetPkgTokenSpaceGuid.PcdMonolithicCapsuleUpdateSupported|FALSE|BOOLEAN|0x40000068
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gChipsetPkgTokenSpaceGuid.PcdTcssPartialUpdateEnable|FALSE|BOOLEAN|0x40000058
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#[-start-210910-QINGLIN0061-modify]#
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# gChipsetPkgTokenSpaceGuid.PcdH2OPreferDtpmBootSupported|TRUE|BOOLEAN|0x4000004C
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gChipsetPkgTokenSpaceGuid.PcdH2OPreferDtpmBootSupported|FALSE|BOOLEAN|0x4000004C
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#[-end-210910-QINGLIN0061-modify]#
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gChipsetPkgTokenSpaceGuid.PcdH2OPeiCpBssbDebugIndicationSupported|TRUE|BOOLEAN|0x40000059
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gChipsetPkgTokenSpaceGuid.PcdH2ODxeCpEcGetSendGetUsciVerSupported|TRUE|BOOLEAN|0x4000005A
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gChipsetPkgTokenSpaceGuid.PcdH2OSmmCpEcSendEspiClearSupported|TRUE|BOOLEAN|0x4000005B
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gChipsetPkgTokenSpaceGuid.PcdH2OPeiCpBiosGuardEcSupported|FALSE|BOOLEAN|0x4000005C
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gChipsetPkgTokenSpaceGuid.PcdH2OPeiCpBiosGuardUpdateBgpdt|FALSE|BOOLEAN|0x40000045
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gChipsetPkgTokenSpaceGuid.PcdUefiWirelessCnvtEnable |TRUE|BOOLEAN|0x4000005D
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## Indicates whether LevelEdge data will be restored or not when S3 resume.
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# TRUE - Restore LevelEdge data.
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# FALSE - Does not restore LevelEdge data.
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# @Prompt Support save/restore for LevelEdge.
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gChipsetPkgTokenSpaceGuid.PcdH2OS3SaveRestoreLevelEdgeSupported|FALSE|BOOLEAN|0x40000060
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## Indicates whether EDP data will be restored or not when S3 resume.
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# TRUE - Restore EDP data.
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# FALSE - Does not restore EDP data.
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# @Prompt Support save/restore for EDP.
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gChipsetPkgTokenSpaceGuid.PcdH2OS3SaveRestoreEDPRegSupported|FALSE|BOOLEAN|0x40000061
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## Indicates whether PIC data will be restored or not when S3 resume.
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# TRUE - Restore PIC data.
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# FALSE - Does not restore PIC data.
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# @Prompt Support save/restore for PIC.
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gChipsetPkgTokenSpaceGuid.PcdH2OS3SaveRestorePicSupported|FALSE|BOOLEAN|0x40000062
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## Indicates whether DMA data will be restored or not when S3 resume.
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# TRUE - Restore DMA data.
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# FALSE - Does not restore DMA data.
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# @Prompt Support save/restore for DMA.
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gChipsetPkgTokenSpaceGuid.PcdH2OS3DmaInitSupported|FALSE|BOOLEAN|0x40000063
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gChipsetPkgTokenSpaceGuid.PcdRetimerCapsuleUpdateSupported|TRUE|BOOLEAN|0x40000064
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gChipsetPkgTokenSpaceGuid.PcdTbtRetimerGetVerDuringBoot|FALSE|BOOLEAN|0x40000065
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[PcdsFixedAtBuild]
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# gino: EDK2 add >>
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#
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# CCEO-0016: RoyalParkOverrideBegin
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#
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## Specifies shadow stack size in bytes for each processor in SMM.
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# @Prompt Processor shadow stack size in SMM.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E
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#
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# CCEO-0016: RoyalParkOverrideEnd
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#
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#
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# CCEO-0016: RoyalParkOverrideBegin
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#
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## Indicates the control flow enforcement enabling state.
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# If enabled, it uses control flow enforcement technology to prevent ROP or JOP.<BR><BR>
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# BIT0 - SMM CET Shadow Stack is enabled.<BR>
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# Other - reserved
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# @Prompt Enable control flow enforcement.
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gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask|0x0|UINT32|0x30001017
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#
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# CCEO-0016: RoyalParkOverrideEnd
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#
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# gino: EDK2 add <<
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#
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# gPlatformModuleTokenSpaceGuid start (Sync with AlderLakePlatSamplePkg\PlatformPkg.dec)
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#
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##
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## The default value for I2C touch device, they will be updated if report descriptor
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## includes the information about them.
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##
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#
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# gPlatformModuleTokenSpaceGuid end
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#
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# gSiPkgTokenSpaceGuid.PcdCflCpuEnable|FALSE|BOOLEAN|0x40000051
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gChipsetPkgTokenSpaceGuid.PcdTxtPublicBase|0xFED30000|UINT32|0x30000011
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gChipsetPkgTokenSpaceGuid.PcdSmmDataPort|0xb3|UINT16|0x30000003
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gChipsetPkgTokenSpaceGuid.PcdSmmActivationData|0x55|UINT8|0x30000004
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gChipsetPkgTokenSpaceGuid.PcdPchGpioBaseAddress|0x800|UINT16|0x30000005
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gChipsetPkgTokenSpaceGuid.PcdTdsEnable|FALSE|BOOLEAN|0xF00000A0
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# Modify the VMD port configuration via SCU default value.
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# TRUE - Change VMD port configuration via SCU default setting (.HFR file).
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# FALSE - CRB default algorithm. The VMD port configuration cannot be modified by .HFR file.
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# VMD port configuration only be modified after end user entering SCU and changing the setting.
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# @Prompt Modify the VMD port configuration via SCU default value.
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gChipsetPkgTokenSpaceGuid.PcdModifyVmdPortConfigViaScuDefault|FALSE|BOOLEAN|0x3000006
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#
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# The PCD for XhciSmiDispatcher, used to control the add-on USB 3.0 card platform specific setting
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#
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# Bit 0 : The flag to skip xHCI hand-off signal
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# Bit 1 : The flag to inverse the SMI signal. 0 = high active, 1 = low active
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# Bit 8 ~ 15 : the number of SMI GPIO pin
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# Bit 16 ~ 23 : The PCI express function number for USB 3.0 add-on card
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# Bit 24 ~ 31 : The PCI express device number for USB 3.0 add-on card
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#
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# e.g. device number is 1C
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# function numbe is 0
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# SMI GPIO pin is GPIO_SKL_LP_GPP_E2
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# SMI signal is low active
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# Enable xHCI hand-off signal
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# gChipsetPkgTokenSpaceGuid.PcdXhciAddonCardSetting|0x1C000C03
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gChipsetPkgTokenSpaceGuid.PcdXhciAddonCardSetting|0x00000000|UINT32|0x30000100
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gChipsetPkgTokenSpaceGuid.PcdPciExpressMaxBusNumber|0xFF|UINT8|0x60000000
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gChipsetPkgTokenSpaceGuid.PcdFlashFvEcBase|0x00000000|UINT32|0x6000001a
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gChipsetPkgTokenSpaceGuid.PcdFlashFvEcSize|0x00000000|UINT32|0x6000001b
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gChipsetPkgTokenSpaceGuid.PcdFlashFvBackupBase|0x00000000|UINT32|0x60000013
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gChipsetPkgTokenSpaceGuid.PcdFlashFvBackupSize|0x00000000|UINT32|0x60000014
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gChipsetPkgTokenSpaceGuid.PcdPciExpressSize|256|UINT16|0x60000015
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gChipsetPkgTokenSpaceGuid.PcdFlashFirmwareBinariesFvBase|0x00000000|UINT32|0x60000016
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gChipsetPkgTokenSpaceGuid.PcdFlashFirmwareBinariesFvSize|0x00000000|UINT32|0x60000017
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gChipsetPkgTokenSpaceGuid.PcdFlashFirmwareBinariesBtGAcmAlignmentOffset|0x00000000|UINT32|0x6000001e
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gChipsetPkgTokenSpaceGuid.PcdFwResiliencyReservedBase|0x00000000|UINT32|0x6000001c
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gChipsetPkgTokenSpaceGuid.PcdFwResiliencyReservedSize|0x00000000|UINT32|0x6000001d
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#[-start-190612-IB16990049-add]#
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gChipsetPkgTokenSpaceGuid.PcdH2OFdmOffset|0x00000000|UINT32|0x60000018
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gChipsetPkgTokenSpaceGuid.PcdH2OFdmSize|0x00000000|UINT32|0x60000019
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#[-end-190612-IB16990049-add]#
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#
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# SIO
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#
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gChipsetPkgTokenSpaceGuid.PcdSioConfigPort|0x002E|UINT16|0x60000023
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gChipsetPkgTokenSpaceGuid.PcdSioIndexPort|0x002E|UINT16|0x60000024
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gChipsetPkgTokenSpaceGuid.PcdSioDataPort|0x002F|UINT16|0x60000025
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# ThunderBolt Gpio Mapping Table
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# ThunderBoltGpioConnectIc 0: PCH 1: SIO
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gChipsetPkgTokenSpaceGuid.PcdThunderBoltGpioConnectIc|0x000000000|UINT8|0x60000026
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# @PcdTypeStruct THUNDERBOLT_GPIO_TO_PCH_DEFINITION {UINT8 TbtGpio2ToPchPin; UINT8 TbtGpio3ToPchPin; UINT8 TbtGpio6ToPchPin; UINT8 TbtGpio7ToPchPin}
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# @PcdTypeArray ThunderBoltGpioToPch THUNDERBOLT_GPIO_TO_PCH_DEFINITION[]
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# @PcdValueType ThunderBoltGpioToPch
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# Assume TBT GPIO 2 3,6,7 is mapped to PCH GPIO 11,12,20,49
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# 0xFF :Unused
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gChipsetPkgTokenSpaceGuid.PcdThunderBoltGpioToPch|{0xff, 18, 0xff, 0xff}|VOID*|0x60000027
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# @PcdTypeStruct THUNDERBOLT_GPIO_TO_SIO_DEFINITION {UINT16 TbtGpio2ToSioGpioSetAddress; UINT16 TbtGpio2ToSioGpioSetAddressBit; UINT16 TbtGpio3ToSioGpioSetAddress; UINT16 TbtGpio3ToSioGpioSetAddressBit; UINT16 TbtGpio6ToSioGpioSetAddress; UINT16 TbtGpio6ToSioGpioSetAddressBit; UINT16 TbtGpio7ToSioGpioSetAddress; UINT16 TbtGpio7ToSioGpioSetAddressBit}
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# @PcdTypeArray ThunderBoltGpioToSio THUNDERBOLT_GPIO_TO_PCH_DEFINITION[]
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# @PcdValueType ThunderBoltGpioToSio
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# Assume TBT GPIO 2 3,6,7 is mapped to SIO/EC GPIO 20,21,40,66,67
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gChipsetPkgTokenSpaceGuid.PcdThunderBoltGpioToSio|{0x01, 0x05, 0, 0, 0x79, 0x03, 0x01, 0x00, 0x03, 0x05, 0, 0, 0x05, 0x05, 0x06, 0x00, 0x05, 0x05, 0x07, 0x00}|VOID*|0x60000028
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# ABAR Hot Capabilites Register (D23:f0)
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# Desktop default: 0xff22ffc2 Mobile default: 0xde127f03 (define on LPT_EDS_Rev1.0.pfd)
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gChipsetPkgTokenSpaceGuid.PcdAbarCapDefault|0xde127f03|UINT32|0x60000029
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gChipsetPkgTokenSpaceGuid.PcdLidStatus|0x00000003|UINT32|0x60000033
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#
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#[-start-190909-IB11270246-add]#
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# XHCI memory space should aligned to 64 KB boundaries. (0x10000)
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#
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gChipsetPkgTokenSpaceGuid.PcdXhciMemBaseAddress|0xD8200000|UINT32|0x60000032
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gChipsetPkgTokenSpaceGuid.PcdCpuXhciMemBaseAddress|0xD8300000|UINT32|0x60000041
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#
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#[-end-190909-IB11270246-add]#
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# PcdPchLpcDecodeRange, used to set LPC Component Decode Range (LPC device offset:80h -81h)
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#
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# bit 2:0 : COMA Decode Range
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# bit 6:4 : COMB Decode Range
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# Value : 000 = 3F8h -3FFh (COM1) 001 = 2F8h -2FFh (COM2)
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# : 010 = 220h -227h 011 = 228h -22Fh
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# : 100 = 238h -23Fh 101 = 2E8h -2EFh (COM4)
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# : 110 = 338h -33Fh 111 = 3E8h -3EFh (COM3)
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# bit 9:8 : LPT Decode Range
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# Value : 00 = 378h-37fh and 778h-77fh 01 = 278h -27Fh (port 279h is ready only) and 678h -67Fh
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# : 10 = 3BCh -3BEh and 7BCh -7BEh
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# bit 12 : FDD Decode Range
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# Value : 0 = 3F0h-3F5h, 3F7h (Primary) 1= 370h -375h, 377h (Secondary)
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gChipsetPkgTokenSpaceGuid.PcdPchLpcDecodeRange|0x0010|UINT16|0x60000034
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#
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# PchLpcEnableList, used to enable/disable LPC Component (LPC device offset:82h-83h)
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#
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# Bit 0 : COMA_LPC_EN Bit 1 : COMB_LPC_EN
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# Bit 2 : LPT_LPC_EN Bit 3 : FDD_LPC_EN
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# Bit 8 : GAMEL_LPC_EN Bit 9 : GAMEH_LPC_EN
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# Bit 10 : KBC_LPC_EN Bit 11 : MC_LPC_EN
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# Bit 12 : CNF1_LPC_EN Bit 13 : CNF2_LPC_EN
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gChipsetPkgTokenSpaceGuid.PcdPchLpcEnableList|0x3F03|UINT16|0x60000035
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#
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# CRB BIOS Enable the LPC I/O decoding for 0x6A0~0x6A7 as EC's extra I/O port, where 0x6A0 is the Data port
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# and 0x6A4 is the Command/Status port.
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#
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gChipsetPkgTokenSpaceGuid.PchLpcGenIoDecodeEcExtraIoPort1|0x06A0|UINT16|0x60000036
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#
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# Provide OemHook to sync HW I2C SCL SDA signal, default value refers to CoffeeLake-H platform
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#
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#[-start-190613-IB16990062-add]#
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gChipsetPkgTokenSpaceGuid.OemHookI2cSclSdaEnable|FALSE|BOOLEAN|0x60000037
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gChipsetPkgTokenSpaceGuid.I2cIcSsSclHcnt|0x01F4|UINT16|0x60000038
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gChipsetPkgTokenSpaceGuid.I2cIcSsSclLcnt|0x024C|UINT16|0x60000039
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gChipsetPkgTokenSpaceGuid.I2cIcSsSdaHold|0x1C|UINT8|0x6000003a
|
|
gChipsetPkgTokenSpaceGuid.I2cIcFsSclHcnt|0x0101|UINT16|0x6000003b
|
|
gChipsetPkgTokenSpaceGuid.I2cIcFsSclLcnt|0x0101|UINT16|0x6000003c
|
|
gChipsetPkgTokenSpaceGuid.I2cIcFsSdaHold|0x1C|UINT8|0x6000003d
|
|
gChipsetPkgTokenSpaceGuid.I2cIcHsSclHcnt|0x0008|UINT16|0x6000003e
|
|
gChipsetPkgTokenSpaceGuid.I2cIcHsSclLcnt|0x0014|UINT16|0x6000003f
|
|
gChipsetPkgTokenSpaceGuid.I2cIcHsSdaHold|0x1C|UINT8|0x60000040
|
|
#[-end-190613-IB16990062-add]#
|
|
|
|
#
|
|
# PeciAccessMethod 0:Direct I/O 1:ACPI
|
|
#
|
|
#
|
|
# File GUIDs definition PCDs
|
|
#
|
|
# GUID Data Structure {UINT32 Data1; UINT16 Data2; UINT16 Data3; UINT8 Data4[8]}
|
|
# PTOpRom.bin - 76824E51-2FA9-433E-980F-B75670E7C5A7
|
|
# Vbt.bin - 878AC2CC-5343-46F2-B563-51F89DAF56BA
|
|
# SLP20Pubkey.bin - 1A1E2341-A2FB-42C7-8D17-3073D08EB21D
|
|
# SLP20Marker.bin - DD6569A7-E455-4EE5-B2BA-ECDA84ACBC99
|
|
# Oa30MsdmData.bin - A9943829-A25A-4B94-AC0B-99DD37099F76
|
|
# LegacyVideo/skl_xxxx_rvp3_rvp7.dat - 8DFAE5D4-B50E-4C10-96E6-F2C266CACBB6
|
|
# LegacyVideo/skl_xxxx_rvp8.dat - ECCCEAAE-E65E-41e9-BD65-CF00FB424641
|
|
# LegacyVideo/skl_xxxx_rvp11.dat - BFEF6019-0E7F-48cb-93D6-1D3E12B4522A
|
|
# LegacyRaidRom/SataOrom.bin - 501737AB-9D1A-4856-86D3-7F1287FA5A55
|
|
# LegacyPxeRom/BA1548L2.bin - 4C316C9A-AFD9-4E33-AEAB-26C4A4ACC0F7
|
|
# LegacyPxeRom/BA1548L2ULT.bin - 72322192-5DEE-4F9C-ADF3-190BD6ADC125
|
|
# VbwOpRom.bin - D3033A61-22AD-4DD8-BB1D-A2EDA0B1C105
|
|
# BiosGuardAcm.bin - 7934156D-CFCE-460E-92F5-A07909A59ECA
|
|
# AnCACM.bin - B42C5280-D6AD-4EDF-871A-77E9DF40F30C
|
|
# OemLogo1024x768.pcx - 6F0CF054-AE6A-418c-A7CE-3C7A7CD74EC0
|
|
# VgaRedir.bin - 346B4547-FEF7-49d4-9A4A-F666825E25B7
|
|
# BiosAc.bin - 2d27c618-7dcd-41f5-bb10-21166be7e143
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdPtOpRomFile|{ 0x51, 0x4E, 0x82, 0x76, 0xA9, 0x2F, 0x3E, 0x43, 0x98, 0x0F, 0xB7, 0x56, 0x70, 0xE7, 0xC5, 0xA7 }|VOID*|0x60000073
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdSlp20PubkeyFile|{ 0x41, 0x23, 0x1E, 0x1A, 0xFB, 0xA2, 0xC7, 0x42, 0x8D, 0x17, 0x30, 0x73, 0xD0, 0x8E, 0xB2, 0x1D }|VOID*|0x60000075
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdSlpP20MarkerFile|{ 0xA7, 0x69, 0x65, 0xDD, 0x55, 0xE4, 0xE5, 0x4E, 0xB2, 0xBA, 0xEC, 0xDA, 0x84, 0xAC, 0xBC, 0x99 }|VOID*|0x60000076
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdOa30MsdmDataFile|{ 0x29, 0x38, 0x94, 0xA9, 0x5A, 0xA2, 0x94, 0x4B, 0xAC, 0x0B, 0x99, 0xDD, 0x37, 0x09, 0x9F, 0x76 }|VOID*|0x60000077
|
|
# @PcdValueType GUID
|
|
# gChipsetPkgTokenSpaceGuid.PcdLegacyRaidRomFile|{ 0xAB, 0x37, 0x17, 0x50, 0x1A, 0x9D, 0x56, 0x48, 0x86, 0xD3, 0x7F, 0x12, 0x87, 0xFA, 0x5A, 0x55 }|VOID*|0x60000079
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdLegacyPxeRomFile|{ 0x9A, 0x6C, 0x31, 0x4C, 0xD9, 0xAF, 0x33, 0x4E, 0xAE, 0xAB, 0x26, 0xC4, 0xA4, 0xAC, 0xC0, 0xF7 }|VOID*|0x6000007A
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdVbiosOpRomFile|{ 0x61, 0x3A, 0x03, 0xD3, 0xAD, 0x22, 0xD8, 0x4D, 0xBB, 0x1D, 0xA2, 0xED, 0xA0, 0xB1, 0xC1, 0x05 }|VOID*|0x6000007B
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdVbtRvp3Rvp7File|{ 0xCC, 0xC2, 0x8A, 0x87, 0x43, 0x53, 0xF2, 0x46, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA }|VOID*|0x6000007C
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdVbtRvp10File|{ 0x06, 0x23, 0x48, 0xDE, 0x4E, 0x0F, 0xBD, 0x43, 0xB3, 0x2D, 0x79, 0x4C, 0x91, 0x4C, 0x02, 0x23 }|VOID*|0x6000007D
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdVbtRvp11File|{ 0xB0, 0x46, 0x4B, 0x13, 0xAF, 0xF5, 0x63, 0x42, 0x97, 0x92, 0xC5, 0xE8, 0x8A, 0x4E, 0xFA, 0x02 }|VOID*|0x6000007E
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdVbtRvp8File|{ 0x58, 0x4B, 0xCD, 0xAF, 0xBA, 0xD4, 0x88, 0x43, 0x94, 0x44, 0x17, 0x42, 0xB9, 0x91, 0xB5, 0xC5 }|VOID*|0x6000007F
|
|
# @PcdValueType GUID
|
|
# gChipsetPkgTokenSpaceGuid.PcdLegacyUltPxeRomFile|{ 0x92, 0x21, 0x32, 0x72, 0xEE, 0x5D, 0x9C, 0x4F, 0xAD, 0xF3, 0x19, 0x0B, 0xD6, 0xAD, 0xC1, 0x25 }|VOID*|0x60000080
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdLegacyAhciRomFile|{ 0x9D, 0xC0, 0x17, 0xB0, 0xC1, 0xED, 0x40, 0x49, 0xB1, 0x3E, 0x57, 0xE9, 0x56, 0x60, 0xC9, 0x0F }|VOID*|0x60000081
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardAcmFile|{ 0x6D, 0x15, 0x34, 0x79, 0xCE, 0xCF, 0x0E, 0x46, 0x92, 0xF5, 0xA0, 0x79, 0x09, 0xA5, 0x9E, 0xCA }|VOID*|0x60000082
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdAnCACMFile|{ 0x80, 0x52, 0x2C, 0xB4, 0xAD, 0xD6, 0xDF, 0x4E, 0x87, 0x1A, 0x77, 0xE9, 0xDF, 0x40, 0xF3, 0x0C }|VOID*|0x60000083
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdOemLogoRomFile|{ 0x54, 0xF0, 0x0C, 0x6F, 0x6A, 0xAE, 0x8C, 0x41, 0xA7, 0XCE, 0x3C, 0x7A, 0x7C, 0xD7, 0x4E, 0xC0 }|VOID*|0x60000084
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdVgaRedirRomFile|{ 0x47, 0x45, 0x6B, 0x34, 0xF7, 0xFE, 0xD4, 0x49, 0x9A, 0x4A, 0xF6, 0x66, 0x82, 0x5E, 0x25, 0xB7 }|VOID*|0x60000085
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosAcRomFile|{ 0x18, 0xC6, 0x27, 0x2D, 0xCD, 0x7D, 0xF5, 0x41, 0xBB, 0x10, 0x21, 0x16, 0x6B, 0xE7, 0xE1, 0x43 }|VOID*|0x60000086
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdBootGuardAcmPadFile|{ 0x55, 0xC6, 0x27, 0x2D, 0xCD, 0x7D, 0xF5, 0x41, 0xBB, 0x10, 0x21, 0x16, 0x6B, 0xE7, 0xE1, 0x43 }|VOID*|0x60000087
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdFitTableReservedFile|{ 0xAA, 0xC6, 0x27, 0x2D, 0xCD, 0x7D, 0xF5, 0x41, 0xBB, 0x10, 0x21, 0x16, 0x6B, 0xE7, 0xE1, 0x43 }|VOID*|0x60000088
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdGop1021VbtRvp3Rvp7File|{ 0x87, 0x7D, 0xD5, 0x01, 0xFF, 0xD8, 0x62, 0x46, 0xA8, 0xC2, 0x3E, 0xAC, 0x91, 0xE9, 0x43, 0xDD }|VOID*|0x62000089
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdGop1021VbtRvp10File|{ 0xE8, 0x05, 0xA3, 0xA5, 0xA8, 0x1A, 0x38, 0x45, 0x9B, 0x08, 0x31, 0xD1, 0x88, 0x47, 0xDF, 0xE6 }|VOID*|0x62000090
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdGop1021VbtRvp8File|{ 0xC5, 0xF2, 0x79, 0x9F, 0x1D, 0xCD, 0x02, 0x4C, 0xA2, 0x1B, 0xE6, 0x5B, 0x6A, 0x59, 0x2B, 0x21 }|VOID*|0x62000092
|
|
# @PcdValueType GUID FF0C8745-3270-4439-B74F-3E45F8C77064
|
|
gChipsetPkgTokenSpaceGuid.PcdVbtRvpFile|{ 0xC5, 0xF2, 0x79, 0x9F, 0x1D, 0xCD, 0x02, 0x4C, 0xA2, 0x1B, 0x3E, 0x45, 0xF8, 0xC7, 0x70, 0x64 }|VOID*|0x62000093
|
|
#[-start-190611-IB16990042-add]#
|
|
# @PcdValueType GUID SinitModuleGuid
|
|
gChipsetPkgTokenSpaceGuid.PcdSinitAcRomFile|{ 0xe4, 0x9f, 0xb8, 0x3f, 0xc5, 0xcf, 0x54, 0x4c ,0x9e, 0xee, 0xe3, 0xdf, 0x01, 0x6e, 0x32, 0x69 }|VOID*|0x62000094
|
|
#[-end-190611-IB16990042-add]#
|
|
# gSbbDigestGuid
|
|
gChipsetPkgTokenSpaceGuid.PcdChasmFallSbbDigestFile|{ 0xA8, 0x2C, 0xDA, 0xB2, 0x59, 0x72, 0x79, 0x4F, 0x64, 0xA4, 0xF7, 0x12, 0x62, 0x5E, 0xD2, 0xC9 }|VOID*|0x62000095
|
|
gChipsetPkgTokenSpaceGuid.PcdChasmFallBiosGuardPbbFile|{ 0xF4, 0x81, 0x14, 0xDD, 0xF9, 0x12, 0x69, 0x4D, 0xAC, 0x11, 0x85, 0x5F, 0xFA, 0xC3, 0x28, 0x16 }|VOID*|0x62000096
|
|
gChipsetPkgTokenSpaceGuid.PcdChasmFallBiosGuardPbbrFile|{ 0x81, 0xD7, 0x70, 0x93, 0x98, 0xEC, 0x3C, 0x4D, 0xB8, 0x8B, 0xF8, 0x67, 0x6A, 0x54, 0xBD, 0xEA }|VOID*|0x62000097
|
|
gChipsetPkgTokenSpaceGuid.PcdChasmFallBiosGuardSbbFile|{ 0x67, 0x48, 0x91, 0x36, 0xBB, 0x7E, 0x12, 0x4C, 0xA7, 0xBA, 0xBA, 0x51, 0x19, 0x1B, 0x04, 0x24 }|VOID*|0x62000098
|
|
#
|
|
# PcdXtuControlIdBuffersize = XTU control ID count * sizeof(CONTROLID_DATA)
|
|
# PcdXtuControlIdBuffersizeInBits = PcdXtuControlIdBuffersize * 8
|
|
# Reference 'Xtudxe.c'
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdXtuControlIdBuffersize|1372|UINT16|0x60000089
|
|
gChipsetPkgTokenSpaceGuid.PcdXtuControlIdBuffersizeInBits|10976|UINT16|0x60000090
|
|
#
|
|
# PcdXmpDataBuffersize = XTU XMP Data Count * sizeof(XMP_DISPLAY_VALUE)
|
|
# PcdXmpDataBuffersizeHalfInBit = (PcdXmpDataBuffersize/2) * 8
|
|
# Reference 'Xtudxe.c'
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdXmpDataBuffersize|208|UINT16|0x60000091
|
|
gChipsetPkgTokenSpaceGuid.PcdXmpDataBuffersizeHalfInBits|0x2C0|UINT16|0x60000092
|
|
#[-start-190909-IB11270246-add]#
|
|
gChipsetPkgTokenSpaceGuid.PcdNvmeMemBaseAddress|0xD9000000|UINT32|0x60000094
|
|
gChipsetPkgTokenSpaceGuid.PcdNvmeRootPortAddress|0x00000000|UINT32|0x60000095
|
|
#[-end-190909-IB11270246-add]#
|
|
#
|
|
# ComponentSize 0: 512KB;1: 1MB , 2: 2MB; 3: 4MB , 4: 8MB;5: 16MB , 6: 32MB;7: 64MB , 8: 128MB;
|
|
#
|
|
## Progress Code for PC_BOOT_OPTION.
|
|
# PROGRESS_CODE_SW_DXE_BS_PC_BOOT_OPTION_CHANGE = (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_DXE_BS_PC_BOOT_OPTION_CHANGE) = 0x03051007
|
|
## SetSsidSvidDxe.c
|
|
#
|
|
# The PCD for SetSsidSvidDxe, used to distinguish add-in cards.
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdNoBridgeDeviceSsid|FALSE|BOOLEAN|0x61000034
|
|
gEfiTraceHubTokenSpaceGuid.PcdTraceHubStatusCodeMaster|0x20|UINT8|0x61000037
|
|
gEfiTraceHubTokenSpaceGuid.PcdTraceHubStatusCodeChannel|0xD|UINT8|0x61000038
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdLegacyVideoRomRvp3Rvp7File|{ 0xD4, 0xE5, 0xFA, 0x8D, 0x0E, 0xB5, 0x10, 0x4C, 0x96, 0xE6, 0xF2, 0xC2, 0x66, 0xCA, 0xCB, 0xB6 }|VOID*|0x61000041
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdLegacyVideoRomRvp8File|{ 0xae, 0xea, 0xcc, 0xec, 0x5e, 0xe6, 0xe9, 0x41, 0xbd, 0x65, 0xcf, 0x00, 0xfb, 0x42, 0x46, 0x41 }|VOID*|0x61000042
|
|
# @PcdValueType GUID
|
|
gChipsetPkgTokenSpaceGuid.PcdLegacyVideoRomRvp11File|{ 0x19, 0x60, 0xef, 0xbf, 0x7f, 0x0e, 0xcb, 0x48, 0x93, 0xd6, 0x1d, 0x3e, 0x12, 0xb4, 0x52, 0x2a }|VOID*|0x61000043
|
|
#[-start-190612-IB16990056-add]#
|
|
# @PcdValueType GUID
|
|
# gChipsetPkgTokenSpaceGuid.PcdLegacyVideoRomIclUltFile|{0x99, 0xd1, 0xa9, 0xe2, 0xa0, 0x2b, 0x4c, 0x0c, 0x9e, 0xfa, 0x2c, 0x5c, 0xd8, 0xd7, 0x27, 0xd2 }|VOID*|0x61000044
|
|
#[-end-190612-IB16990056-add]#
|
|
gChipsetPkgTokenSpaceGuid.PcdPciDeviceFilterOutTable|0|UINT32|0x2000009c
|
|
gChipsetPkgTokenSpaceGuid.PcdForcMebxSyncUp|0|UINT32|0x2000009d
|
|
## PchPolicy.h
|
|
#
|
|
# PinSelection GpioC 0:GPIO37; 1:GPIO4
|
|
# GpioD 0:GPIO5 ; 1:GPIO0
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdPchMemoryThrottlingEnable|TRUE|BOOLEAN|0x200000a0
|
|
gChipsetPkgTokenSpaceGuid.PcdPchMemoryThrottlingTsGpioPinSettingTsGpioCPmsyncEnable|TRUE|BOOLEAN|0x200000a1
|
|
gChipsetPkgTokenSpaceGuid.PcdPchMemoryThrottlingTsGpioPinSettingTsGpioDPmsyncEnable|TRUE|BOOLEAN|0x200000a2
|
|
gChipsetPkgTokenSpaceGuid.PcdPchMemoryThrottlingTsGpioPinSettingTsGpioCC0TransmitEnable|TRUE|BOOLEAN|0x200000a3
|
|
gChipsetPkgTokenSpaceGuid.PcdPchMemoryThrottlingTsGpioPinSettingTsGpioDC0TransmitEnable|TRUE|BOOLEAN|0x200000a4
|
|
gChipsetPkgTokenSpaceGuid.PcdPchMemoryThrottlingTsGpioPinSettingTsGpioCPinSelection|0x00000001|UINT8|0x200000a5
|
|
gChipsetPkgTokenSpaceGuid.PcdPchMemoryThrottlingTsGpioPinSettingTsGpioDPinSelection|0x00000000|UINT8|0x200000a6
|
|
#
|
|
# ApicRangeSelect Define address bits 19:12 for the IOxAPIC range
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdPchIoApicConfigApicRangeSelect|0x00000000|UINT8|0x200000c1
|
|
#
|
|
# SmmBwp 0: Clear SMM_BWP bit; 1: Set SMM_BWP bit
|
|
#
|
|
# This policy has to be set to 0 (disabled) if customer does use
|
|
# PchSpiRuntime driver instead of PchSpiSmm driver.
|
|
## CpuPolicy.h
|
|
#
|
|
# CpuPlatformPolicyPpi
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdPowerMgmtConfigTccActivationOffset|0x00000000|UINT8|0x200000f0
|
|
gChipsetPkgTokenSpaceGuid.PcdTxtConfigSinitMemorySize|0x50000|UINT32|0x200000f1
|
|
gChipsetPkgTokenSpaceGuid.PcdTxtConfigTxtHeapMemorySize|0xE0000|UINT32|0x200000f2
|
|
gChipsetPkgTokenSpaceGuid.PcdTxtConfigTgaSize|0|UINT32|0x200000f3
|
|
gChipsetPkgTokenSpaceGuid.PcdTxtConfigTxtLcpPdBase|0|UINT32|0x200000f4
|
|
gChipsetPkgTokenSpaceGuid.PcdTxtConfigTxtLcpPdSize|0|UINT32|0x200000f5
|
|
#
|
|
# PowerMgmtConfigVrCurrentLimit use VR_CURRENT_DEFAULT 0x0
|
|
#
|
|
#
|
|
# SpdProfile 0: Default SPD; 1: XMP Profile 1; 2: XMP Profile 2; 3: User defined profile
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdMemConfigMrcTimeMeasure|0x00000000|UINT8|0x200001bb
|
|
#
|
|
# MrcUltPoSafeConfig 1 to enable, 0 to disable
|
|
# DqPinsInterleaved Interleaving mode of DQ/DQS pins for HSW_ULT which depends on board routing
|
|
gChipsetPkgTokenSpaceGuid.PcdMemConfigDqPinsInterleaved|TRUE|BOOLEAN|0x200001c6
|
|
gChipsetPkgTokenSpaceGuid.PcdIuerStatusVal|0x00|UINT8|0x200001c9
|
|
#
|
|
# Initialize the Hybrid Graphics Feature Configuration.
|
|
# ==========================================================================
|
|
# || Gpin Pin Name || Gpio Pin || Active || In/Out || PCD Name ||
|
|
# ==========================================================================
|
|
# || dGPU_HOLD_RST || 0x06020005 || LOW || OUTPUT || HgDgpuHoldRst ||
|
|
# || dGPU_PWR_EN || 0x0600000E || LOW || OUTPUT || HgDgpuPwrEnable ||
|
|
# ==========================================================================
|
|
# GpioSupport - If project doesn't use any GPIO pin to control MXM dGPU,
|
|
# it can set to FALSE to disable.
|
|
# Value - GPIO pin Value, it should be set base on project GPIOs design.
|
|
# Active - FALSE(0):Low Active, TRUE(1):High Active
|
|
# Exist - FALSE(0):This pin doesn't exist, TRUE(1):This pin exist.
|
|
# CRB default has these pins, it can be disable base on project GPIOs design.
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdUseCrbHgDefaultSettings|TRUE|BOOLEAN|0x2000020d
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuGpioSupport|TRUE|BOOLEAN|0x2000020e
|
|
#[start-210731-STORM1101-modify]#
|
|
# gChipsetPkgTokenSpaceGuid.PcdHgDgpuWakeGpioNo|0|UINT32|0x2000020f
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuWakeGpioNo|0x09020014|UINT32|0x2000020f
|
|
#[end-210731-STORM1101-modify]#
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuPwrOkGpioNo|0x09020013|UINT32|0x20000210
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuPwrOkActive|TRUE|BOOLEAN|0x20000211
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuPwrOkExist|FALSE|BOOLEAN|0x20000212
|
|
#[start-210731-STORM1101-modify]#
|
|
# gChipsetPkgTokenSpaceGuid.PcdHgDgpuHoldRstGpioNo|0x09000002|UINT32|0x20000213
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuHoldRstGpioNo|0x0902000F|UINT32|0x20000213
|
|
#[end-210731-STORM1101-modify]#
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuHoldRstActive|FALSE|BOOLEAN|0x20000214
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuSelGpioNo|0|UINT32|0x20000215
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuSelActive|FALSE|BOOLEAN|0x20000216
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuSelExist|FALSE|BOOLEAN|0x20000217
|
|
#[start-210731-STORM1101-modify]#
|
|
# gChipsetPkgTokenSpaceGuid.PcdHgDgpuPwrEnableGpioNo|0x0902000E|UINT32|0x20000218
|
|
# gChipsetPkgTokenSpaceGuid.PcdHgDgpuPwrEnableActive|FALSE|BOOLEAN|0x20000219
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuPwrEnableGpioNo|0x090E000A|UINT32|0x20000218
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuPwrEnableActive|TRUE|BOOLEAN|0x20000219
|
|
#[end-210731-STORM1101-modify]#
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuEdidSelGpioNo|0|UINT32|0x2000021a
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuEdidSelActive|FALSE|BOOLEAN|0x2000021b
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuEdidSelExist|FALSE|BOOLEAN|0x2000021c
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuPwmSelGpioNo|0|UINT32|0x2000021d
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuPwmSelActive|FALSE|BOOLEAN|0x2000021e
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuPwmSelExist|FALSE|BOOLEAN|0x2000021f
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuPrsntGpioNo|0|UINT32|0x20000220
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuPrsntActive|FALSE|BOOLEAN|0x20000221
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpuPrsntExist|FALSE|BOOLEAN|0x20000222
|
|
#
|
|
# Slave MXM GPU GPIO pin related setting, CRB default set same with master GPU.
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2GpioSupport|FALSE|BOOLEAN|0x20000223
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2WakeGpioNo|0|UINT32|0x20000224
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2PwrOkGpioNo|0|UINT32|0x20000225
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2PwrOkActive|TRUE|BOOLEAN|0x20000226
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2HoldRstGpioNo|0|UINT32|0x20000227
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2HoldRstActive|FALSE|BOOLEAN|0x20000228
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2PwrEnableGpioNo|0|UINT32|0x20000229
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2PwrEnableActive|FALSE|BOOLEAN|0x2000022a
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2PrsntGpioNo|0|UINT32|0x2000022b
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2PrsntActive|FALSE|BOOLEAN|0x2000022c
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2PrsntExist|FALSE|BOOLEAN|0x2000022d
|
|
#
|
|
# Set Master and Slave DGPU bridge bus/device/function, Secondary Grcphics Command Register.
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdHgPegBridgeBus|0|UINT8|0x2000022e
|
|
gChipsetPkgTokenSpaceGuid.PcdHgPegBridgeDevice|1|UINT8|0x2000022f
|
|
gChipsetPkgTokenSpaceGuid.PcdHgPegBridgeFunction|0|UINT8|0x20000230
|
|
gChipsetPkgTokenSpaceGuid.PcdHgPcieBridgeBus|0|UINT8|0x20000231
|
|
#[-start-190612-IB16990054-add]#
|
|
gChipsetPkgTokenSpaceGuid.PcdHgPcieRootPortIndex|4|UINT8|0x2000024e
|
|
#[-end-190612-IB16990054-add]#
|
|
# gChipsetPkgTokenSpaceGuid.PcdHgPcieBridgeDevice|28|UINT8|0x20000232
|
|
# gChipsetPkgTokenSpaceGuid.PcdHgPcieBridgeFunction|0|UINT8|0x20000233
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2BridgeBus|0|UINT8|0x20000234
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2BridgeDevice|1|UINT8|0x20000235
|
|
gChipsetPkgTokenSpaceGuid.PcdHgDgpu2BridgeFunction|1|UINT8|0x20000236
|
|
gChipsetPkgTokenSpaceGuid.PcdAmdSecondaryGrcphicsCommandRegister|0|UINT8|0x20000237
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaSecondaryGrcphicsCommandRegister|6|UINT8|0x20000238
|
|
#
|
|
# Set MXM SIS and HG SSDT GUID when need another MXM SIS or SSDT.
|
|
# File GUIDs definition PCDs (MasterMxm30.bin - 6135A10D-9126-4a7f-B07C-E157ADE9ACE1)
|
|
# AmdDiscreteSsdt - 50F6366B-0BF7-4aab-89A5-A17AF863806B
|
|
# AmdPowerXpressSsdt - 76AED82E-77DE-42ca-8C27-E9D71DF606C7
|
|
# AmdPowerUltXpressSsdt - AB698DB2-8896-444e-A854-597C5B1879BB
|
|
# NvidiaOptimusSsdtN18 - 7E1CABE3-34D8-4f54-831C-9E1D52F48F8E
|
|
# NvidiaDiscreteSsdtN18 - 662D072E-70A0-4e14-901F-8DB301631647
|
|
# NvidiaUltOptimusSsdtN18 - 7A614C58-7DF7-4423-B243-094CD6125A44
|
|
# NvidiaUltDiscreteSsdtN18 - 5660b63b-2ed5-43f2-92ba-a74346d806be
|
|
# NvidiaOptimusSsdtN17 - 8E1CABE3-34D8-4f54-831C-9E1D52F48F8E
|
|
# NvidiaDiscreteSsdtN17 - 762D072E-70A0-4e14-901F-8DB301631647
|
|
# NvidiaUltOptimusSsdtN17 - 8A614C58-7DF7-4423-B243-094CD6125A44
|
|
# NvidiaUltDiscreteSsdtN17 - 6660b63b-2ed5-43f2-92ba-a74346d806be
|
|
# NvidiaOptimusSsdtN20 - 828c7930-d180-4a11-90a2-cac747b33918
|
|
# NvidiaDiscreteSsdtN20 - a761fee1-3847-4315-b74b-065762ba1bf5
|
|
# NvidiaUltOptimusSsdtN20 - c4e12756-6a74-4b39-8206-3ed6d3a590b0
|
|
# NvidiaUltDiscreteSsdtN20 - 5668caa7-a56e-45d3-a6f7-07f0c773c31d
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdHgModeMxmBinaryGuid|{ 0x0D, 0xA1, 0x35, 0x61, 0x26, 0x91, 0x7f, 0x4a, 0xB0, 0x7C, 0xE1, 0x57, 0xAD, 0xE9, 0xAC, 0xE1 }|VOID*|0x20000239
|
|
gChipsetPkgTokenSpaceGuid.PcdPegModeMasterMxmBinaryGuid|{ 0x0D, 0xA1, 0x35, 0x61, 0x26, 0x91, 0x7f, 0x4a, 0xB0, 0x7C, 0xE1, 0x57, 0xAD, 0xE9, 0xAC, 0xE1 }|VOID*|0x2000023a
|
|
gChipsetPkgTokenSpaceGuid.PcdPegModeSlaveMxmBinaryGuid|{ 0x0D, 0xA1, 0x35, 0x61, 0x26, 0x91, 0x7f, 0x4a, 0xB0, 0x7C, 0xE1, 0x57, 0xAD, 0xE9, 0xAC, 0xE1 }|VOID*|0x2000023b
|
|
gChipsetPkgTokenSpaceGuid.PcdAmdDiscreteSsdtGuid|{ 0x6B, 0x36, 0xF6, 0x50, 0xF7, 0x0B, 0xab, 0x4a, 0x89, 0xA5, 0xA1, 0x7A, 0xF8, 0x63, 0x80, 0x6B }|VOID*|0x2000023c
|
|
gChipsetPkgTokenSpaceGuid.PcdAmdPowerXpressSsdtGuid|{ 0x2E, 0xD8, 0xAE, 0x76, 0xDE, 0x77, 0xca, 0x42, 0x8C, 0x27, 0xE9, 0xD7, 0x1D, 0xF6, 0x06, 0xC7 }|VOID*|0x2000023d
|
|
gChipsetPkgTokenSpaceGuid.PcdAmdUltPowerXpressSsdtGuid|{ 0xB2, 0x8D, 0x69, 0xAB, 0x96, 0x88, 0x4E, 0x44, 0xA8, 0x54, 0x59, 0x7C, 0x5B, 0x18, 0x79, 0xBB }|VOID*|0x2000023e
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaOptimusSsdtN18Guid|{ 0xE3, 0xAB, 0x1C, 0x7E, 0xD8, 0x34, 0x54, 0x4f, 0x83, 0x1C, 0x9E, 0x1D, 0x52, 0xF4, 0x8F, 0x8E }|VOID*|0x2000023f
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaDiscreteSsdtN18Guid|{ 0x2E, 0x07, 0x2D, 0x66, 0xA0, 0x70, 0x14, 0x4e, 0x90, 0x1F, 0x8D, 0xB3, 0x01, 0x63, 0x16, 0x47 }|VOID*|0x20000240
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaUltOptimusSsdtN18Guid|{ 0x58, 0x4C, 0x61, 0x7A, 0xF7, 0x7D, 0x23, 0x44, 0xB2, 0x43, 0x09, 0x4C, 0xD6, 0x12, 0x5A, 0x44 }|VOID*|0x20000241
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaUltDiscreteSsdtN18Guid|{ 0x3b, 0xb6, 0x60, 0x56, 0xd5, 0x2e, 0xf2, 0x43, 0x92, 0xba, 0xa7, 0x43, 0x46, 0xd8, 0x06, 0xbe }|VOID*|0x2000024d
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaOptimusSsdtN17Guid|{ 0xE3, 0xAB, 0x1C, 0x8E, 0xD8, 0x34, 0x54, 0x4f, 0x83, 0x1C, 0x9E, 0x1D, 0x52, 0xF4, 0x8F, 0x8E }|VOID*|0x2000024f
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaDiscreteSsdtN17Guid|{ 0x2E, 0x07, 0x2D, 0x76, 0xA0, 0x70, 0x14, 0x4e, 0x90, 0x1F, 0x8D, 0xB3, 0x01, 0x63, 0x16, 0x47 }|VOID*|0x20000250
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaUltOptimusSsdtN17Guid|{ 0x58, 0x4C, 0x61, 0x8A, 0xF7, 0x7D, 0x23, 0x44, 0xB2, 0x43, 0x09, 0x4C, 0xD6, 0x12, 0x5A, 0x44 }|VOID*|0x20000251
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaUltDiscreteSsdtN17Guid|{ 0x3b, 0xb6, 0x60, 0x66, 0xd5, 0x2e, 0xf2, 0x43, 0x92, 0xba, 0xa7, 0x43, 0x46, 0xd8, 0x06, 0xbe }|VOID*|0x20000252
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaOptimusSsdtN20Guid|{ 0x30, 0x79, 0x8c, 0x82, 0x80, 0xd1, 0x11, 0x4a, 0x90, 0xa2, 0xca, 0xc7, 0x47, 0xb3, 0x39, 0x18 }|VOID*|0x20000270
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaDiscreteSsdtN20Guid|{ 0xe1, 0xfe, 0x61, 0xa7, 0x47, 0x38, 0x15, 0x43, 0xb7, 0x4b, 0x06, 0x57, 0x62, 0xba, 0x1b, 0xf5 }|VOID*|0x20000271
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaUltOptimusSsdtN20Guid|{ 0x56, 0x27, 0xe1, 0xc4, 0x74, 0x6a, 0x39, 0x4b, 0x82, 0x06, 0x3e, 0xd6, 0xd3, 0xa5, 0x90, 0xb0 }|VOID*|0x20000272
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaUltDiscreteSsdtN20Guid|{ 0xa7, 0xca, 0x68, 0x56, 0x6e, 0xa5, 0xd3, 0x45, 0xa6, 0xf7, 0x07, 0xf0, 0xc7, 0x73, 0xc3, 0x1d }|VOID*|0x20000273
|
|
#
|
|
# nVIDIA detail related feature flag
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdHgNvidiaOptimusDgpuHotPlugSupport|TRUE|BOOLEAN|0x20000242
|
|
gChipsetPkgTokenSpaceGuid.PcdHgNvidiaOptimusDgpuPowerControlSupport|TRUE|BOOLEAN|0x20000243
|
|
gChipsetPkgTokenSpaceGuid.PcdHgNvidiaGpsFeatureSupport|TRUE|BOOLEAN|0x20000244
|
|
gChipsetPkgTokenSpaceGuid.PcdHgNvidiaVenturaFeatureSupport|FALSE|BOOLEAN|0x20000245
|
|
gChipsetPkgTokenSpaceGuid.PcdHgNvidiaNbciFeatureSupport|FALSE|BOOLEAN|0x20000246
|
|
gChipsetPkgTokenSpaceGuid.PcdHgNvidiaOptimusGc6FeatureSupport|FALSE|BOOLEAN|0x20000247
|
|
gChipsetPkgTokenSpaceGuid.PcdHgNvidiaOptimusGc6NvsrFeatureSupport|FALSE|BOOLEAN|0x20000248
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaGC6FBEN|0|UINT32|0x20000249
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaGPUEvent|0|UINT32|0x2000024a
|
|
gChipsetPkgTokenSpaceGuid.PcdHgNvidiaDgpuCheckTable|{0}|VOID*|0x20000253
|
|
gChipsetPkgTokenSpaceGuid.PcdHgNvidiaDgpuCheckTable2|{0, 0}|VOID*|0x20000260
|
|
## Indicates if the platform can support NV GC6 v3.0 or not.
|
|
# TRUE - Supports GC6 v3.0.
|
|
# FALSE - Supports GC6 v2.x.
|
|
# @Prompt Enable NV GC6 v3.0 support.
|
|
gChipsetPkgTokenSpaceGuid.PcdHgNvidiaOptimusGc6V30Support|TRUE|BOOLEAN|0x2000024b
|
|
## Indicates if the platform can support NVPCF or not.
|
|
# TRUE - Supports NVPCF.
|
|
# FALSE - Not supports NVPCF.
|
|
# @Prompt Enalbe NVPCF support.
|
|
gChipsetPkgTokenSpaceGuid.PcdHgNvidiaNpcfFeatureSupport|FALSE|BOOLEAN|0x2000024c
|
|
|
|
#
|
|
# Nvidia DDS feature: PCH GPIO for display switch MUX.
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaDDSMuxModePin|0|UINT32|0x20000254
|
|
|
|
#
|
|
# Nvidia DDS feature: PCH GPIO for LCD force reset pin.
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdNvidiaDDSLcdForceResetPin|0|UINT32|0x20000255
|
|
|
|
|
|
## Indicates Intel DG1 VRAM Self Refresh GPIO pin.
|
|
# @Prompt DG1 VRAM SR GPIO pin.
|
|
gChipsetPkgTokenSpaceGuid.PcdIntelDg1VramSrGpioNo|0|UINT32|0x20000256
|
|
|
|
#
|
|
# Firmware capsule guid
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsMeFirmwareCapsuleGuid|{ 0x2C, 0x32, 0x5D, 0x86, 0xC7, 0x6A, 0x34, 0x47, 0xB4, 0x3E, 0x55, 0xDB, 0x5A, 0x55, 0x7D, 0x63 }|VOID*|0x20000264
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsIshFirmwareCapsuleGuid|{ 0xEA, 0x4C, 0x8B, 0x97, 0x60, 0x7C, 0xF8, 0x41, 0xB5, 0xDD, 0x93, 0x79, 0x7F, 0xD3, 0xF3, 0x14 }|VOID*|0x20000265
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsPdtFirmwareCapsuleGuid|{ 0x32, 0xE3, 0x25, 0xC7, 0x08, 0x8C, 0x0B, 0x45, 0x97, 0xBA, 0x57, 0xCC, 0xCF, 0xA0, 0xDA, 0x35 }|VOID*|0x20000266
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsEcFirmwareCapsuleGuid|{ 0xFA, 0x8A, 0x89, 0xA9, 0x58, 0xEF, 0xFE, 0x48, 0xB0, 0x9A, 0xF4, 0x76, 0xAF, 0xCE, 0x46, 0x7C }|VOID*|0x20000267
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsIomFirmwareCapsuleGuid|{ 0xAA, 0xF0, 0xE0, 0x02, 0x45, 0x5D, 0x4D, 0xFF, 0xAB, 0x90, 0x78, 0x58, 0xE5, 0x12, 0x95, 0x12 }|VOID*|0x20000268
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsMgPhyFirmwareCapsuleGuid|{ 0xF2, 0x0F, 0x43, 0x48, 0x6A, 0xE3, 0x46, 0x2F, 0xB1, 0x4d, 0xCA, 0xE6, 0xC3, 0xE4, 0xD4, 0xE6 }|VOID*|0x20000269
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsTbtFirmwareCapsuleGuid|{ 0xDB, 0xB0, 0x2D, 0xDB, 0x36, 0x72, 0x49, 0x90, 0x9F, 0xA2, 0x53, 0xF5, 0x83, 0x4D, 0x19, 0x76 }|VOID*|0x2000026A
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsUcodeFirmwareCapsuleGuid| {0xC2, 0x8C, 0xC6, 0xB9, 0x96, 0x20, 0x46, 0xA8, 0xA7, 0x43, 0xE8, 0xC2 , 0x79, 0x5D, 0x97, 0xC9 }|VOID*|0x2000002E
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsBtGAcmFirmwareCapsuleGuid| {0x9D, 0x50, 0x8A, 0x3B, 0x4A, 0xEF, 0x0A, 0x4E, 0xBE, 0x64, 0x6A, 0x45, 0xF9, 0x03, 0xC3, 0x8C }|VOID*|0x2000026B
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsMonolithicFirmwareCapsuleGuid|{0xCE, 0xD1, 0x3B, 0x99, 0xD4, 0x03, 0x47, 0x77, 0x85, 0x65, 0x7E, 0xBB, 0x67, 0xB7, 0x14, 0xFE}|VOID*|0x20000274
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsTbtRetimer1FirmwareCapsuleGuid|{ 0x90, 0xF0, 0x2A, 0x83, 0xF9, 0x2E, 0x47, 0x7C, 0x8F, 0x6D, 0xB4, 0x05, 0xC8, 0xC7, 0xF1, 0x56 }|VOID*|0x2000026C
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsTbtRetimer2FirmwareCapsuleGuid|{ 0x08, 0x41, 0xEF, 0x20, 0x64, 0x6C, 0x49, 0xD0, 0xB6, 0xDE, 0x11, 0xEE, 0x35, 0x98, 0x0B, 0x8F }|VOID*|0x2000026D
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsTbtRetimer3FirmwareCapsuleGuid|{ 0x33 ,0xBF, 0x28, 0x27, 0xFA, 0xA3, 0x44, 0xF7, 0xB0, 0x41, 0x9F, 0x70, 0xEB, 0x73, 0xD2, 0x3E }|VOID*|0x2000026E
|
|
gChipsetPkgTokenSpaceGuid.PcdWindowsTbtRetimer4FirmwareCapsuleGuid|{ 0xF5, 0x9B, 0x49, 0x49, 0x84, 0xE8, 0x4A, 0x79, 0xA9, 0xC2, 0xF3, 0x1D, 0xC0, 0x5A, 0x04, 0x96 }|VOID*|0x2000026F
|
|
#
|
|
# Please don't change the default value of EndOfPostDone and the value will be updated to 1 when EOP has been sent to ME FW successfully.
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdIsvtInfoSmbiosType|0x000000DE|UINT8|0x20000356
|
|
#
|
|
# FviSmbiosType is the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS Type 14 - Group
|
|
# Associations structure - item type. FVI structure uses it as SMBIOS OEM type to provide
|
|
# version information. The default value is type 221.
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdMeMiscConfigFviSmbiosType|0x000000DD|UINT8|0x20000357
|
|
#
|
|
# Intel Silicon View Technology (ISVT) IO Reading port 0x99 with
|
|
# AH = 0x10 for "Memory Init Complete"
|
|
# 0x20 for "End of DXE Phase"
|
|
# 0x30 for "BIOS Boot Complete"
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdIsvtCheckPointIoReadPort|153|UINT16|0x2000035A # 0x99
|
|
gChipsetPkgTokenSpaceGuid.PcdIsvtCheckPoint1AhPreloadValue|0x10|UINT8|0x2000035B
|
|
gChipsetPkgTokenSpaceGuid.PcdIsvtCheckPoint2AhPreloadValue|0x00000020|UINT8|0x2000035C
|
|
gChipsetPkgTokenSpaceGuid.PcdIsvtCheckPoint3AhPreloadValue|0x00000030|UINT8|0x2000035D
|
|
gChipsetPkgTokenSpaceGuid.PcdIsvtCheckPointCount|0x00000003|UINT8|0x2000035E
|
|
#
|
|
# While BiosLock is enabled, BIOS can only be modified from SMM after ExitPmAuth.
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdPchLockDownConfigBiosLock|0x00000001|UINT8|0x20000362
|
|
#
|
|
# If PchBiosLockIoTrapAddress is 0, BIOS will allocate available IO address with
|
|
# 256 byte range from GCD and pass it to PchBiosLockIoTrapAddress.
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdPchLockDownConfigPchBiosLockIoTrapAddress|0x00000000|UINT16|0x20000363
|
|
gChipsetPkgTokenSpaceGuid.PcdPchDeviceEnablingDisplay|0x00000001|UINT8|0x20000365
|
|
#
|
|
# 0: PchSataSpeedSupportDefault 1: PchSataSpeedSupportGen1, 2: PchSataSpeedSupportGen2, 3: PchSataSpeedSupportGen3
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdPchIoApicConfigBdfValid|TRUE|BOOLEAN|0x20000390
|
|
gChipsetPkgTokenSpaceGuid.PcdPchIoApicConfigBusNumber|0x000000F0|UINT8|0x20000391
|
|
gChipsetPkgTokenSpaceGuid.PcdPchIoApicConfigDeviceNumber|0x0000001F|UINT8|0x20000392
|
|
gChipsetPkgTokenSpaceGuid.PcdPchIoApicConfigFunctionNumber|0x00000000|UINT8|0x20000393
|
|
#
|
|
# for Ult
|
|
#
|
|
#
|
|
# 0: PchLpssIs33V , 1: PchLpssIs18V
|
|
#
|
|
#
|
|
# 0: PcieAspmDisabled, 1: PcieAspmL0s, 2: PcieAspmL1, 3: PcieAspmL0sL1, 4: PcieAspmAutoConfig,
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdIccPlatformPolicyIccDefaultProfile|0x000000000|UINT8|0x20000409
|
|
gChipsetPkgTokenSpaceGuid.PcdIccPlatformPolicyFunctionEnablingFcim|0x000000001|UINT32|0x2000040a
|
|
gChipsetPkgTokenSpaceGuid.PcdSaPciePwrOptLtrMaxSnoopLatency|0x0846|UINT16|0x20000412
|
|
gChipsetPkgTokenSpaceGuid.PcdSaPciePwrOptLtrMaxNoSnoopLatency|0x0846|UINT16|0x20000413
|
|
gChipsetPkgTokenSpaceGuid.PcdSaPciePwrOptObffEnable|0x01|UINT8|0x20000414
|
|
#
|
|
# UpdateAcpiTable.c
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdPs2MouseEnable|1|UINT8|0x20000490
|
|
gChipsetPkgTokenSpaceGuid.PcdGpe0BlkOffset|0x80|UINT8|0x20000491
|
|
gChipsetPkgTokenSpaceGuid.PcdGpe0BlkLen|0x20|UINT8|0x20000492
|
|
gChipsetPkgTokenSpaceGuid.PcdCmosIndexPort|0x70|UINT8|0x20000493
|
|
gChipsetPkgTokenSpaceGuid.PcdCmosDataPort|0x71|UINT8|0x20000494
|
|
gChipsetPkgTokenSpaceGuid.PcdPlatformDebugPort|0x80|UINT8|0x20000495
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OPort80DebugEnable|1|UINT8|0x20000496
|
|
gChipsetPkgTokenSpaceGuid.PcdEfiPort80DebugEnable|0|UINT8|0x20000497
|
|
gChipsetPkgTokenSpaceGuid.PcdDsdtRevision|0x1|UINT8|0x20000498
|
|
gChipsetPkgTokenSpaceGuid.PcdDebugSizeMask|0xFFF|UINT32|0x20000499
|
|
gChipsetPkgTokenSpaceGuid.PcdDebugSize|0x1000|UINT32|0x2000049A
|
|
#
|
|
# If SCU Enable 10s Power Button Override
|
|
# set Bit0: 10 sec P-button Enable/Disable,
|
|
# and Bit7: EC 10sec PB Override state for S3/S4 wake up.
|
|
# Else Clear 10s Power Button Enable and Override bits.
|
|
#
|
|
#
|
|
# Note: If change sizeof(SYSTEM_CONFIGURATION) in SetupConfig.h, must update really structure size in Project.dsc!!!
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdSetupConfigSize|1200|UINT32|0x70000013
|
|
#
|
|
# OEM specific items
|
|
#
|
|
#
|
|
# Configure I2C Sensor Hub: (0)Unknown (1)Intel (2)I2C STM
|
|
#
|
|
# PcdSaveCmosFieldCompareList
|
|
# @PcdTypeStruct CMOS_ELEMENT {UINT8 Start_Offset; UINT8 Lenght;} " this sturcture is for Save Cmos compare table"
|
|
# @PcdValueType CMOS_ELEMENT[]
|
|
gChipsetPkgTokenSpaceGuid.PcdSaveCmosFieldCompareList|{0}|VOID*|0x20000519
|
|
gChipsetPkgTokenSpaceGuid.PcdSaMiscConfigUserBd|5|UINT8|0x20000520
|
|
gChipsetPkgTokenSpaceGuid.PcdSmbiosType20PartitionRowPosition|0xFF|UINT8|0x20000539
|
|
#
|
|
# TRUE - Daylight Savings feature is ALWAYS DISABLED, regardless of the setting in RTC_REGB.DSE.
|
|
# FALSE - Daylight Savings feature is dependent on Daylight Savings Enable bit located at RTC_REGB.DSE.
|
|
#
|
|
|
|
# ED RAM BAR
|
|
# KBL-CPU:0xFED80000, CNL-CPU:0xFED80000
|
|
gChipsetPkgTokenSpaceGuid.PcdSaEdRamBaseAddress|0xFED80000|UINT32|0x20000607
|
|
gChipsetPkgTokenSpaceGuid.PcdSaTsegSize|0x1000000|UINT32|0x20000608
|
|
gChipsetPkgTokenSpaceGuid.PcdIedSize|0x400000|UINT32|0x20000609
|
|
gChipsetPkgTokenSpaceGuid.PcdSaGdxcBaseAddress|0xFED84000|UINT32|0x2000060A
|
|
gChipsetPkgTokenSpaceGuid.PcdSaPcieConfigPegGpioDataSaPegResetActive|0x00|UINT8|0x20000626
|
|
# GpioSupport 1=Supported; 0=Not Supported
|
|
# SaPegReset PEG PERST# GPIO assigned
|
|
# Value GPIO Value
|
|
# Active 0=Active Low; 1=Active High
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdSaMemConfigPowerDownMode|0xFF|UINT8|0x2000062B
|
|
gChipsetPkgTokenSpaceGuid.PcdSaMemConfigRankInterleave|0x01|UINT8|0x2000062D
|
|
gChipsetPkgTokenSpaceGuid.PcdSaMemConfigEnhancedInterleave|0x01|UINT8|0x2000062E
|
|
gChipsetPkgTokenSpaceGuid.PcdSaMemConfigEnCmdRate|0x07|UINT8|0x2000062F
|
|
gChipsetPkgTokenSpaceGuid.PcdSaMemConfigAutoSelfRefreshSupport|TRUE|BOOLEAN|0x20000630
|
|
gChipsetPkgTokenSpaceGuid.PcdSaMemConfigExtTemperatureSupport|TRUE|BOOLEAN|0x20000631
|
|
#
|
|
# 0 - Disabled, 1 - GDXC IOT/MOT, 2 - HD Port
|
|
#
|
|
# 100 * 1000 * 1000
|
|
gChipsetPkgTokenSpaceGuid.PcdSaMemConfigBClkFrequency|0x05F5E100|UINT32|0x20000657
|
|
gChipsetPkgTokenSpaceGuid.PcdSaMemConfigForce1Dpc|TRUE|BOOLEAN|0x20000658
|
|
gChipsetPkgTokenSpaceGuid.PcdSaMemConfigPciIndex|0xCF8|UINT16|0x2000065F
|
|
gChipsetPkgTokenSpaceGuid.PcdSaMemConfigPciData|0xCFC|UINT16|0x20000660
|
|
gChipsetPkgTokenSpaceGuid.PcdSaMemConfigCkeRankMapping|0xAA|UINT8|0x20000661
|
|
gChipsetPkgTokenSpaceGuid.PcdSiTempPciBusMin|0x00000002|UINT8|0x20000680
|
|
gChipsetPkgTokenSpaceGuid.PcdSiTempPciBusMax|0x00000010|UINT8|0x20000681
|
|
gChipsetPkgTokenSpaceGuid.PcdPchLpPcieConfigRootPortLtrMaxSnoopLatency|0x1003|UINT16|0x20000694
|
|
gChipsetPkgTokenSpaceGuid.PcdPchLpPcieConfigRootPortLtrMaxNoSnoopLatency|0x1003|UINT16|0x20000695
|
|
gChipsetPkgTokenSpaceGuid.PcdPchHPcieConfigRootPortLtrMaxSnoopLatency|0x0846|UINT16|0x20000696
|
|
gChipsetPkgTokenSpaceGuid.PcdPchHPcieConfigRootPortLtrMaxNoSnoopLatency|0x0846|UINT16|0x20000697
|
|
gChipsetPkgTokenSpaceGuid.PcdPcieConfigRootPortSnoopLatencyOverrideMode|2|UINT8|0x20000698
|
|
gChipsetPkgTokenSpaceGuid.PcdPcieConfigRootPortSnoopLatencyOverrideMultiplier|2|UINT8|0x20000699
|
|
gChipsetPkgTokenSpaceGuid.PcdPcieConfigRootPortSnoopLatencyOverrideValue|60|UINT16|0x2000069A
|
|
gChipsetPkgTokenSpaceGuid.PcdPcieConfigRootPortNonSnoopLatencyOverrideMode|2|UINT8|0x2000069B
|
|
#
|
|
# ApicRangeSelect Define address bits 19:12 for the IOxAPIC range
|
|
# IoApicEntry24_119 0: Disable; 1: Enable IOAPIC Entry 24-119
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdPchIoApicConfigIoApicId|0x00000002|UINT8|0x200006B0
|
|
# Must be at least 521us (25 frames)
|
|
gChipsetPkgTokenSpaceGuid.PcdPchAzaliaPolicyPpiResetWaitTimer|600|UINT16|0x200006B2
|
|
gChipsetPkgTokenSpaceGuid.PcdPchDeviceEnablingSmbus|TRUE|BOOLEAN|0x200006B3
|
|
gChipsetPkgTokenSpaceGuid.PcdPchLockDownConfigBiosInterface|0x00000001|UINT8|0x200006B4
|
|
gChipsetPkgTokenSpaceGuid.PcdPchLockDownConfigGlobalSmi|0x00000001|UINT8|0x200006B5
|
|
gChipsetPkgTokenSpaceGuid.PcdThermalAlertEnableTsmicLock|1|UINT8|0x200006B6
|
|
gChipsetPkgTokenSpaceGuid.PcdThermalThrottlingTTLevelsSuggestedSetting|0x00000001|UINT8|0x200006B7
|
|
gChipsetPkgTokenSpaceGuid.PcdThermalThrottlingDmiHaAWCSuggestedSetting|0x00000001|UINT8|0x200006B9
|
|
gChipsetPkgTokenSpaceGuid.PcdPchPowerResetStatusClearMeWakeSts|0x00000001|UINT8|0x200006BB
|
|
gChipsetPkgTokenSpaceGuid.PcdPchPowerResetStatusClearMeHrstColdSts|0x00000001|UINT8|0x200006BC
|
|
gChipsetPkgTokenSpaceGuid.PcdPchPowerResetStatusClearMeHrstWarmSts|0x00000001|UINT8|0x200006BD
|
|
gChipsetPkgTokenSpaceGuid.PcdPchPowerResetStatusClearWolOvrWkSts|0x00000001|UINT8|0x200006BE
|
|
gChipsetPkgTokenSpaceGuid.PcdPchPmConfigSlpS0Enable|TRUE|BOOLEAN|0x200006BF
|
|
gChipsetPkgTokenSpaceGuid.PcdSerialIrqConfigSirqEnable|TRUE|BOOLEAN|0x200006C1
|
|
gChipsetPkgTokenSpaceGuid.PcdSerialIrqConfigStartFramePulse|0x00000000|UINT8|0x200006C2
|
|
gChipsetPkgTokenSpaceGuid.PcdPchInterruptConfigSciIrqSelect|9|UINT8|0x200006D5
|
|
gChipsetPkgTokenSpaceGuid.PcdPchInterruptConfigTcoIrqSelect|9|UINT8|0x200006D6
|
|
gChipsetPkgTokenSpaceGuid.PcdHpetConfigEnable|0x00000001|UINT32|0x200006DC
|
|
#
|
|
# VrMiscIoutSlope = 0x200 default
|
|
# VrMiscIoutOffsetSign = 0 means it's positive offset. 1= negative offset
|
|
# VrMiscIoutOffset = 0 means it's 0%, 625 means 6.25% (range is +6.25% ~ -6.25%)
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdPpmLockEnablesPmgCstCfgCtrlLock|0x00000001|UINT32|0x20000713
|
|
|
|
#
|
|
# Bios Guard prevent back-flashing.
|
|
# The ESRT Version is similar as the BIOS version.
|
|
# If Project.dsc didn't re-defined the PcdBiosGuardConfigBgpdtBiosSvn.
|
|
# Default will reference ESRT Version for Bios Guard to do the back-flashing compare.
|
|
# PcdBiosGuardConfigBgpdtBiosSvn and BiosSvn in BiosGuardSetting.ini will be updated autometically in the build time.
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigBgpdtBiosSvn|0x00000000|UINT32|0x20000724
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigBgpdtPublicKeySlot0|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x2000072F
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigBgpdtPublicKeySlot1|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x20000730
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigBgpdtPublicKeySlot2|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x20000731
|
|
#
|
|
# For EC
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigEcCmdDiscovery|0x00|UINT8|0x20000727
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigEcCmdProvisionEav|0x00|UINT32|0x20000728
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigEcCmdLock|0x00|UINT32|0x20000729
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigBgpdtEcCmdGetSvn|0x00|UINT32|0x2000072A
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigBgpdtEcCmdOpen|0x00|UINT32|0x2000072B
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigBgpdtEcCmdClose|0x00|UINT32|0x2000072C
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigBgpdtEcCmdPortTest|0x00|UINT32|0x2000072D
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigBgupHeaderEcSvn|0x00000000|UINT32|0x2000072E
|
|
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashFvRecovery0Base|0x00000000|UINT32|0x20000774
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashFvRecovery0Size|0x00000000|UINT32|0x20000775
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashFvRecovery2Base|0x00000000|UINT32|0x20000776
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashFvRecovery2Size|0x00000000|UINT32|0x20000777
|
|
gChipsetPkgTokenSpaceGuid.PcdSecureFlashWakeFromS3Time|3|UINT8|0x20001001
|
|
|
|
#FSPTODO:
|
|
# This PCD is automatically updated by FspBinFvsBaseAddress.exe. Please do NOT modify !!!
|
|
# gChipsetPkgTokenSpaceGuid.PcdFsptBaseAddress|0xFFFB6000|UINT32|0x2000077E
|
|
# gChipsetPkgTokenSpaceGuid.PcdFspmBaseAddress|0xFFEA3000|UINT32|0x2000077F
|
|
# gChipsetPkgTokenSpaceGuid.PcdFspsBaseAddress|0xFFE40000|UINT32|0x20000770
|
|
|
|
##
|
|
## ME firmware update reserved memory size
|
|
##
|
|
gChipsetPkgTokenSpaceGuid.PcdMeFirmwareUpdateReservedMemorySize|0x00000000|UINT32|0x20000790
|
|
|
|
#[-start-190606-IB16990032-add]#
|
|
## This value is used to pass Device ID list to SA NVS
|
|
gChipsetPkgTokenSpaceGuid.PcdSaGlobalNvsDeviceId|{0}|VOID*|0x20000027
|
|
#[-end-190606-IB16990032-add]#
|
|
|
|
# Intel ChasmFalls feature
|
|
# 0 - Not support ChasmFalls feature
|
|
# 1 - Support ChasmFalls gen 1
|
|
# 2 - Support ChasmFalls gen 2
|
|
gChipsetPkgTokenSpaceGuid.PcdChasmFallsSupport|0|UINT8|0x2000002C
|
|
gChipsetPkgTokenSpaceGuid.VariableFlashReservedBase|0x00000000|UINT32|0x20000791
|
|
gChipsetPkgTokenSpaceGuid.VariableFlashReservedSize|0x00000000|UINT32|0x20000792
|
|
|
|
## Indicates the maximum number of Non-CPU PCIe root port in all platform SKUs
|
|
# Ex: The numbers of PCH PCIe root port on Tiger Lake platform:
|
|
# ADL - P -> 12
|
|
# ADL - S -> 28 (Maxumum number)
|
|
# @Prompt the maximum number of Non-CPU PCIe root port in all platform SKUs
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OPcieNonCpuPortNumber|0|UINT8|0x2000002F
|
|
|
|
#
|
|
# Bus[0~7] Device[8~15] Function[16~23] Port[24~31]
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdTbtRetimerAddress|0x00000000|UINT32|0x1000100E
|
|
gChipsetPkgTokenSpaceGuid.PcdTbtRetimerDefaultVersion|0x0000|UINT16|0x1000100F
|
|
|
|
# Insyde PCD controls Native FSP build,
|
|
# It means your FSP binary builds by Insyde or Intel
|
|
# TRUE - Use Intel Native FSP.
|
|
# FALSE - Insyde BIOS should build FSP.
|
|
gChipsetPkgTokenSpaceGuid.PcdNativeFspBuild|FALSE|BOOLEAN|0x20000030
|
|
gChipsetPkgTokenSpaceGuid.PcdNativeFspVersion|""|VOID*|0x20000031
|
|
|
|
#
|
|
# PCH PCIE HSIO Setting
|
|
# Please reference Intel\AlderLake\ClientOneSiliconPkg\Fru\AdlPch\LibraryPrivate\FiaSocLib\FiaSocLibAdlP.c
|
|
# PchFiaGetPcieLaneNum() for Index<->Lane mapping
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioRxSetCtleEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x20000032
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioRxSetCtle |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x20000033
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioTxGen1DownscaleAmpEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x20000034
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioTxGen1DownscaleAmp |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x20000035
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioTxGen2DownscaleAmpEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x20000036
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioTxGen2DownscaleAmp |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x20000037
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioTxGen3DownscaleAmpEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x20000038
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioTxGen3DownscaleAmp |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x20000039
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioTxGen1DeEmphEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x2000003A
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioTxGen1DeEmph |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x2000003B
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioTxGen2DeEmph3p5Enable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x2000003C
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioTxGen2DeEmph3p5 |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x2000003D
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioTxGen2DeEmph6p0Enable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x2000003E
|
|
gChipsetPkgTokenSpaceGuid.PchPcieHsioTxGen2DeEmph6p0 |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x2000003F
|
|
|
|
#
|
|
# PCH USB3 HSIO Setting
|
|
# Please reference Intel\AlderLake\ClientOneSiliconPkg\Fru\AdlPch\LibraryPrivate\FiaSocLib\FiaSocLibAdlP.c
|
|
# PchFiaGetUsb3LaneNum() for Index <-> Lane mapping
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioTxDownscaleAmp |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000040
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioTxDeEmph |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000041
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioCtrlAdaptOffsetCfg |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000042
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioFilterSelN |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000043
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioFilterSelP |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000044
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioOlfpsCfgPullUpDwnRes |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000045
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioTxDeEmphEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000046
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioTxDownscaleAmpEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000047
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioCtrlAdaptOffsetCfgEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000048
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioFilterSelNEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000049
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioFilterSelPEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x2000004A
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioOlfpsCfgPullUpDwnResEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x2000004B
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioTxRate3UniqTran |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x2000004C
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioTxRate2UniqTran |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x2000004D
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioTxRate1UniqTran |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x2000004E
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioTxRate0UniqTran |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x2000004F
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioTxRate3UniqTranEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000050
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioTxRate2UniqTranEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000051
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioTxRate1UniqTranEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000052
|
|
gChipsetPkgTokenSpaceGuid.PchUsb3HsioTxRate0UniqTranEnable |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0x20000053
|
|
|
|
[PcdsDynamicEx]
|
|
gH2ODeviceInfo2TokenSpaceGuid.PcdH2ODeviceInfoOnboradXhci|{0}|VOID*|0x10000001
|
|
gH2ODeviceInfo2TokenSpaceGuid.PcdH2ODeviceInfoOnboradAhci|{0}|VOID*|0x10000002
|
|
gH2ODeviceInfo2TokenSpaceGuid.PcdH2ODeviceInfoOnboradEmmc|{0}|VOID*|0x10000003
|
|
gH2ODeviceInfo2TokenSpaceGuid.PcdH2ODeviceInfoOnboradSd|{0}|VOID*|0x10000004
|
|
gH2ODeviceInfo2TokenSpaceGuid.PcdH2ODeviceInfoM2Nvme|{0}|VOID*|0x10000005
|
|
gH2ODeviceInfo2TokenSpaceGuid.PcdH2ODeviceInfoCpuM2Nvme|{0}|VOID*|0x10000006
|
|
gH2ODeviceInfo2TokenSpaceGuid.PcdH2ODeviceInfoCpuM2Nvme2|{0}|VOID*|0x10000007
|
|
|
|
# @PcdTypeStruct EFI_SIO_TABLE {UINT8 Register; UINT8 Value} "This structure is for SIO table"
|
|
# @PcdTypeArray PeiSioTable EFI_SIO_TABLE[ ] "SIO table data."
|
|
# @PcdValueType PeiSioTable
|
|
gChipsetPkgTokenSpaceGuid.PcdPeiSioTable|{0}|VOID*|0x70000007
|
|
# PcdPeiXXXXGpioTableN (where XXXX is the device, empty = chipset) and N is the instance (1,2,3)
|
|
# @PcdTypeStruct EFI_SIO_GPIO_TABLE {UINT8 Register; UINT8 Value} "This structure is for SIO GPIO table"
|
|
# @PcdTypeArray PeiSioGpioTable1 EFI_SIO_GPIO_TABLE[] "SIO GPIO table data"
|
|
# @PcdValueType PeiSioGpioTable1
|
|
gChipsetPkgTokenSpaceGuid.PcdPeiSioGpioTable1|{0}|VOID*|0x70000008
|
|
#
|
|
# PcdPchLpcIoDecodeTable, used to set LPC I/F Generic Decode Range (LPC device offset:84h-93h)
|
|
#
|
|
# @PcdTypeStruct IO_DECODE_TABLE {UINT16 Address; UINT16 Length} "Bit 15:2 Decode Range Base Address, Bit 23:18 Decode Range address [7:2]Mask"
|
|
# @PcdTypeArray PchLpcGenIoDecodeTable IO_DECODE_TABLE[] "LPC I/F Generic Decode Range data"
|
|
# @PcdValueType PchLpcGenIoDecodeTable
|
|
gChipsetPkgTokenSpaceGuid.PcdPchLpcGenIoDecodeTable|{0}|VOID*|0x70000009
|
|
|
|
#
|
|
# BoardId
|
|
#
|
|
# This PCD will auto patch by build process, should not be modified.
|
|
gChipsetPkgTokenSpaceGuid.PcdCrbBoard|TRUE|BOOLEAN|0x7000000A
|
|
|
|
# If customer added the Board ID into the section of [SkuIds] in project.dsc,
|
|
# Customer should consider three PCD setting as following, otherwise those will not be needed.
|
|
# 1. PcdOemProjectReferenceIntelCrbBoardType
|
|
# 2. PcdOemProjectReferenceIntelCrbBoardPlatformType
|
|
# 3. PcdOemProjectReferenceIntelCrbBoardPlatformFlavor
|
|
#
|
|
# PcdOemProjectReferenceIntelCrbBoardType
|
|
# The value of PCD, Reference PlatformBoardType.h file.
|
|
gChipsetPkgTokenSpaceGuid.PcdOemProjectReferenceIntelCrbBoardType|0xFF|UINT8|0x7100000B
|
|
#
|
|
# PcdOemProjectReferenceIntelCrbBoardPlatformType
|
|
# The value of PCD, Reference PlatformBoardId.h file
|
|
gChipsetPkgTokenSpaceGuid.PcdOemProjectReferenceIntelCrbBoardPlatformType|0xFF|UINT8|0x7100000C
|
|
#
|
|
# PcdOemProjectReferenceIntelCrbBoardPlatformFlavor
|
|
# The value of PCD, Reference PlatformBoardId.h file
|
|
gChipsetPkgTokenSpaceGuid.PcdOemProjectReferenceIntelCrbBoardPlatformFlavor|0xFF|UINT8|0x7100000D
|
|
|
|
# PcdOemProjectReferenceIntelCrbBoardSpdPresent
|
|
# This value of PCD comes from EC, EcBoardInfo.SklFields.SpdPresent.
|
|
gChipsetPkgTokenSpaceGuid.PcdOemProjectReferenceIntelCrbBoardSpdPresent|FALSE|BOOLEAN|0x71000010
|
|
# gChipsetPkgTokenSpaceGuid.PcdOemProjectReferenceIntelCrbBoardBomId|0xFF|UINT8|0x71000011
|
|
|
|
#
|
|
# Gpe.asl _Lxx value will be overwritten in UpdateAcpiTable.c during POST
|
|
# if target machine is ULT platform and PcdOverwriteGpeEventValue is TRUE.
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdDefaultSsidSvidPeiTable|{0}|VOID*|0x70000012
|
|
|
|
gChipsetPkgTokenSpaceGuid.PcdLowestSupportedMeVersion|0x03E8|UINT16|0x70000018
|
|
gChipsetPkgTokenSpaceGuid.PcdLowestSupportedIshVersion|0x03E8|UINT16|0x70000019
|
|
gChipsetPkgTokenSpaceGuid.PcdLowestSupportedEcVersion|0x03E8|UINT16|0x70000024
|
|
gChipsetPkgTokenSpaceGuid.PcdLowestSupportedPdtVersion|0x03E8|UINT16|0x70000025
|
|
gChipsetPkgTokenSpaceGuid.PcdLowestSupportedIomVersion|0x03E8|UINT16|0x70000026
|
|
gChipsetPkgTokenSpaceGuid.PcdLowestSupportedMgPhyVersion|0x03E8|UINT16|0x70000027
|
|
gChipsetPkgTokenSpaceGuid.PcdLowestSupportedTbtVersion|0x03E8|UINT16|0x70000028
|
|
gChipsetPkgTokenSpaceGuid.PcdLowestSupportedBtGAcmVersion|0x03E8|UINT16|0x70000029
|
|
|
|
#
|
|
# For Bios Guard
|
|
# Platform Name
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdBiosGuardConfigBgpdtPlatformId|""|VOID*|0x30000001
|
|
|
|
#
|
|
# OEM Memory Done Support
|
|
# When PcdH2OMemoryDownSupported = TRUE, all the following PCDs should set to proper value base on HW design
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSupported|FALSE|BOOLEAN|0x70000030
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownRcompResistorSupported|FALSE|BOOLEAN|0x70000031
|
|
#[-start-190625-IB06740669-modify]#
|
|
#[-start-200420-IB17800056-modify]#
|
|
# ADL RC change the type
|
|
# gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownRcompResistor|{0}|VOID*|0x70000032
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownRcompResistor|{0}|UINT32|0x70000032
|
|
#[-end-200420-IB17800056-modify]#
|
|
#[-end-190625-IB06740669-modify]#
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownRcompTargetSupported|FALSE|BOOLEAN|0x70000033
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownRcompTarget|{0}|VOID*|0x70000034
|
|
# gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataSupported|FALSE|BOOLEAN|0x70000035
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataChannel0Socket0|{0}|VOID*|0x70000036
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataChannel0Socket1|{0}|VOID*|0x70000037
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataChannel1Socket0|{0}|VOID*|0x70000038
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataChannel1Socket1|{0}|VOID*|0x70000039
|
|
#[-start-200420-IB17800056-modify]#
|
|
#
|
|
# ADL RC change the PCD name
|
|
#
|
|
# gChipsetPkgTokenSpaceGuid.PcdH2OMrcDqByteMapSupported|FALSE|BOOLEAN|0x70000040
|
|
# gChipsetPkgTokenSpaceGuid.PcdH2OMrcDqByteMap|{0}|VOID*|0x70000041
|
|
# gChipsetPkgTokenSpaceGuid.PcdH2OMrcDqsMapCpu2DramSupported|FALSE|BOOLEAN|0x70000042
|
|
# gChipsetPkgTokenSpaceGuid.PcdH2OMrcDqsMapCpu2Dram|{0}|VOID*|0x70000043
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownDqByteMapSupported|FALSE|BOOLEAN|0x70000040
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownDqByteMap|{0}|VOID*|0x70000041
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownDqsMapCpu2DramSupported|FALSE|BOOLEAN|0x70000042
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownDqsMapCpu2Dram|{0}|VOID*|0x70000043
|
|
#[-end-200420-IB17800056-modify]#
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownDqPinsInterleavedSupported|FALSE|BOOLEAN|0x70000044
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownDqPinsInterleaved|TRUE|BOOLEAN|0x70000045
|
|
|
|
#
|
|
# Please use following PCDs to program memorydown SPD when PcdH2OMemoryDownSupported = TRUE
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataMc0Ch0Dimm0|{0}|VOID*|0x70000046
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataMc0Ch1Dimm0|{0}|VOID*|0x70000047
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataMc0Ch2Dimm0|{0}|VOID*|0x70000048
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataMc0Ch3Dimm0|{0}|VOID*|0x70000049
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataMc1Ch0Dimm0|{0}|VOID*|0x70000050
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataMc1Ch1Dimm0|{0}|VOID*|0x70000051
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataMc1Ch2Dimm0|{0}|VOID*|0x70000052
|
|
gChipsetPkgTokenSpaceGuid.PcdH2OMemoryDownSpdDataMc1Ch3Dimm0|{0}|VOID*|0x70000053
|
|
|
|
#
|
|
# Intel platform code uses SkuId for declare U/Y/H SKUs
|
|
# It conflicts with H2O SkuId (PcdH2OBoardId) usage
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdCrbSkuId|0|UINT16|0x70000054
|
|
|
|
gChipsetPkgTokenSpaceGuid.PcdMaxGpioPins|0|UINT16|0x70000055
|
|
|
|
#
|
|
# The PCD which is defined to enable/disable EPI Device (for SDS board).
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPartBaseAddress|0|UINT32|0x00101026
|
|
|
|
gChipsetPkgTokenSpaceGuid.PcdLowestSupportedRetimerVersion|0x03E8|UINT16|0x70000057
|
|
|
|
gChipsetPkgTokenSpaceGuid.PcdOverrideMemorySlotMap|{0}|VOID*|0x71000100
|
|
gChipsetPkgTokenSpaceGuid.PcdOverrideMemorySlotMapEnable|FALSE|BOOLEAN|0x71000101
|
|
|
|
#[-start-211104-IB17040212-add]#
|
|
#
|
|
# This PCD is useing in Tbt retimer get version function CapabilityParsing() Intel WA delay.
|
|
# If need reduce delay time in CapabilityParsing(), can use this PCD to use custom value.
|
|
# 0 = Intel RC default value(2s).
|
|
# Set value in "us" (2s = 2000000us)
|
|
# recommend that not set longer then default value(2s).
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdTbtRetimerCapParsingDelay|0|UINT32|0x40000069
|
|
#[-end-211104-IB17040212-add]#
|
|
|
|
[PcdsDynamic]
|
|
|
|
[PcdsPatchableInModule]
|
|
#[-start-200723-IB10181006-modify]#
|
|
##
|
|
## This PCD is defined in gClientCommonModuleTokenSpaceGuid.
|
|
## RC removed this pkg and no longer use these PCDs.
|
|
## But our "ChipsetPkg\Override\EDK2\PcAtChipsetPkg\Library\TscAcpiTimerLib" still use these.
|
|
## Redefine to chipset PCD.
|
|
##
|
|
## This PCD specifies the recovery image size used for serial recovery.
|
|
## This PCD specifies the ACPI IO base address.
|
|
gChipsetPkgTokenSpaceGuid.PcdAcpiIoBaseAddress|0x1800|UINT16|0x10000021
|
|
## This PCD specifies the length of ACPI Timer. (only 24 and 32 are supported)
|
|
gChipsetPkgTokenSpaceGuid.AcpiTimerLength|24|UINT8|0x10000022
|
|
#[-end-200723-IB10181006-modify]#
|
|
|
|
[PcdsDynamicEx]
|
|
# @PcdTypeStruct LEGACY_MODIFY_PIR_TABLE {UINTN BridgeBus; UINTN BridgeDevice; UINTN BridgeFunction; UINT8 VirtualSecondaryBus;}
|
|
# @PcdTypeArray VirtualBusTable LEGACY_MODIFY_PIR_TABLE[] "An array of PCI bridge"
|
|
# @PcdValueType VirtualBusTable[]
|
|
gChipsetPkgTokenSpaceGuid.PcdVirtualBusTable|{0}|VOID*|0x80000014
|
|
# @PcdTypeStruct EFI_LEGACY_PIRQ_ENTRY {UINT8 Pirq; UINT16 IrqMask;}
|
|
# @PcdTypeStruct EFI_LEGACY_IRQ_ROUTING_ENTRY_AND_IP_REGISTER {EFI_LEGACY_IRQ_ROUTING_ENTRY LeagcyIrqRoutingEntry; UINT32 DevIpRegValue; UINT8 ProgrammableIrq;}
|
|
# @PcdTypeArray PcdControllerDeviceIrqRoutingEntry EFI_LEGACY_IRQ_ROUTING_ENTRY_AND_IP_REGISTER[]; "An array of Controller device IRQ routing entry."
|
|
# @PcdValueType PcdControllerDeviceIrqRoutingEntry[]
|
|
gChipsetPkgTokenSpaceGuid.PcdControllerDeviceIrqRoutingEntry|{0}|VOID*|0x80000015
|
|
# @PcdTypeArray PcdPirqPriorityTable UINT8[]; "An array of PIRQ value."
|
|
# @PcdValueType PcdPirqPriorityTable
|
|
gChipsetPkgTokenSpaceGuid.PcdPirqPriorityTable|{0}|VOID*|0x80000017
|
|
# @PcdTypeStruct EFI_LEGACY_IRQ_PRIORITY_TABLE_ENTRY {UINT8 Irq; UINT8 Used;}
|
|
# @PcdTypeArray PcdIrqPoolTable EFI_LEGACY_IRQ_PRIORITY_TABLE_ENTRY[] ; "An array of IRQ pool."
|
|
# @PcdValueType PcdIrqPoolTable
|
|
gChipsetPkgTokenSpaceGuid.PcdIrqPoolTable|{0}|VOID*|0x80000018
|
|
# @PcdTypeArray PcdPirqLinkValueArray UINT8[]; "An array of PIRQ link Array."
|
|
# @PcdValueType PcdPirqLinkValueArray
|
|
gChipsetPkgTokenSpaceGuid.PcdPirqLinkValueArray|{0}|VOID*|0x80000019
|
|
gChipsetPkgTokenSpaceGuid.Pcd2HControllerDeviceIrqRoutingEntry|{0}|VOID*|0x80000020
|
|
gChipsetPkgTokenSpaceGuid.PcdIntelMeCapsuleUpdateSig|{0xEE, 0x64, 0x13, 0xFF, 0x67, 0xCD, 0x88, 0xFD, 0x13, 0xBA, 0xEC, 0x10, 0xFA, 0x7A, 0xE5, 0xBC}|VOID*|0x80000023
|
|
gI2cDeviceTokenSpaceGuid.PcdI2cTouchpad|{ 0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00, 0x00, 0x00, 0x00,0x00, 0x00,0x00, 0x00, 0x00, 0x00 }|VOID*|0x80000016
|
|
#[-start-210608-BAIN000009-add]#
|
|
gI2cDeviceTokenSpaceGuid.PcdI2cTouchpad1|{ 0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00, 0x00, 0x00, 0x00,0x00, 0x00,0x00, 0x00, 0x00, 0x00 }|VOID*|0x8000002B
|
|
#[-end-210608-BAIN000009-add]#
|
|
|
|
#[-start-210916-xinwei0002-add]#
|
|
gI2cDeviceTokenSpaceGuid.PcdI2cTouchpad2|{ 0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00, 0x00, 0x00, 0x00,0x00, 0x00,0x00, 0x00, 0x00, 0x00 }|VOID*|0x8000002C
|
|
gI2cDeviceTokenSpaceGuid.PcdI2cTouchpad3|{ 0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00, 0x00, 0x00, 0x00,0x00, 0x00,0x00, 0x00, 0x00, 0x00 }|VOID*|0x8000002E
|
|
#[-end-210916-xinwei0002-add]#
|
|
#[-start-210729-Kebin00040-add]#
|
|
gI2cDeviceTokenSpaceGuid.PcdI2cTouchpanel|{ 0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00, 0x00, 0x00, 0x00,0x00, 0x00,0x00, 0x00, 0x00, 0x00 }|VOID*|0x8000002D
|
|
#[-end-210729-Kebin00040-add]#
|
|
# gChipsetPkgTokenSpaceGuid.PcdH2OConsoleRedirectionClassGuid|{0}|VOID*|0x8000002A
|
|
|
|
#
|
|
# MultiBoard: Base and Size for Option ROM
|
|
#
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPciOptionRomBaseRvp3Rvp7|0x00000000|UINT32|0x8000001A
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPciOptionRomSizeRvp3Rvp7|0x00000000|UINT32|0x8000001B
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPciOptionRomBaseRvp8|0x00000000|UINT32|0x8000001C
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPciOptionRomSizeRvp8|0x00000000|UINT32|0x8000001D
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPciOptionRomBaseRvp11|0x00000000|UINT32|0x8000001E
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPciOptionRomSizeRvp11|0x00000000|UINT32|0x8000001F
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPciOptionRomBaseRaid|0x00000000|UINT32|0x80000021
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPciOptionRomSizeRaid|0x00000000|UINT32|0x80000024
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPciOptionRomBase15B804|0x00000000|UINT32|0x80000025
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPciOptionRomSize15B804|0x00000000|UINT32|0x80000026
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPciOptionRomBase157004|0x00000000|UINT32|0x80000027
|
|
gChipsetPkgTokenSpaceGuid.PcdFlashPciOptionRomSize157004|0x00000000|UINT32|0x80000028
|
|
gChipsetPkgTokenSpaceGuid.PcdTDSBlockConInEnable|TRUE|BOOLEAN|0x2000002D
|
|
|
|
[PcdsFixedAtBuild, PcdsPatchableInModule]
|
|
|
|
|
|
[Guids]
|
|
#[-start-200121-IB10189023-add]#
|
|
gSaveIntelRemapDevInfoGuid = { 0xa8588563, 0xe0f9, 0x4dad, {0xab, 0xa0, 0xe2, 0x7a, 0x70, 0xf6, 0x41, 0xa3} }
|
|
#[-end-200121-IB10189023-add]#
|
|
|
|
gOsProfileGuid = {0xe59376d7, 0x2dd9, 0x42a3, {0x9e, 0xc8, 0x1d, 0x71, 0xd5, 0xe3, 0xc1, 0xec}}
|
|
gEfiSystemNvDataHobGuid = {0xd6e5092d, 0xc7b2, 0x4872, {0xaf, 0x66, 0xfd, 0xc0, 0xe6, 0xf9, 0x5e, 0x78}}
|
|
gAttemptUsbFirstHotkeyInfoHobGuid = {0x38b8e214, 0x1468, 0x4bb7, {0x95, 0xb1, 0x74, 0x59, 0x1e, 0x4c, 0x6e, 0x1d}}
|
|
gHaloMd2VariableGuid = {0x4b534b3b, 0x9bdc, 0x4460, {0x93, 0x73, 0x57, 0x2e, 0x48, 0x11, 0xee, 0x83}}
|
|
gPlatformFviSetupGuid = {0xf375cc65, 0x6065, 0x48f3, {0x83, 0x70, 0x6c, 0x65, 0x33, 0x74, 0x1d, 0x3f}}
|
|
gPegConfigVariableGuid = {0xb414caf8, 0x8225, 0x4d6f, {0xb9, 0x18, 0xcd, 0xe5, 0xcb, 0x84, 0xcf, 0x0b}}
|
|
gIntelPeiGraphicsVbtGuid = {0x878AC2CC, 0x5343, 0x46F2, {0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA}}
|
|
gTianoLogoGuid = {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
|
|
gWlanDriverImageGuid = {0x32ea828b, 0x523b, 0x44cb, {0xb7, 0xa4, 0x7e, 0x0a, 0x2a, 0x49, 0x95, 0x6c}}
|
|
gBluetoothHciImageGuid = {0x7DE9DF83, 0x2D2A, 0x4448, {0xA9, 0xB1, 0x7D, 0xA7, 0x51, 0x58, 0x56, 0x2A}}
|
|
# ClientCommonPkg
|
|
gBootStateGuid = { 0x60b5e939, 0x0fcf, 0x4227, { 0xba, 0x83, 0x6b, 0xbe, 0xd4, 0x5b, 0xc0, 0xe3 }}
|
|
gFastBootExceptionInfoHobGuid = { 0x4ed88276, 0xd4df, 0x4d03, { 0x86, 0x61, 0x29, 0x58, 0x01, 0xb2, 0xda, 0x58 }}
|
|
gPlatformInfoHobGuid = { 0x54c61c94, 0x287d, 0x4dc5, { 0x99, 0xd5, 0xd3, 0x8d, 0x1a, 0x53, 0xae, 0x6b }}
|
|
gFastBootFunctionEnabledHobGuid = { 0x019fb1ca, 0xd411, 0x4948, { 0xb7, 0x3c, 0x4c, 0x05, 0x4a, 0xba, 0x9e, 0x8e }}
|
|
gPpamManifestGuid = {0x1878f400, 0xdcdb, 0x4f5e, {0x8b, 0x2d, 0x85, 0x71, 0x4a, 0xca, 0x2c, 0x90}}
|
|
##
|
|
## Intel RST
|
|
##
|
|
gRstConfigVariableGuid = {0x4da4f952, 0x2516, 0x4d06, {0x89, 0x75, 0x65, 0x03, 0x64, 0x03, 0xa8, 0xc7}}
|
|
#
|
|
# Crash Log Support
|
|
#
|
|
gPmcCrashLogDataBufferHobGuid = {0xf3c1138e, 0xcd89, 0x4e20, {0x9e, 0x68, 0x25, 0xa6, 0x76, 0x95, 0xa5, 0x6b}}
|
|
gCpuCrashLogDataBufferHobGuid = {0x09f119d5, 0xa5ad, 0x4b30, {0x90, 0x9e, 0xfa, 0x94, 0xdc, 0xa3, 0xc9, 0xb5}}
|
|
|
|
gEfiFirmwareErrorSectionGuid = {0x81212a96, 0x09ed, 0x4996, {0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed}}
|
|
gSetupVariableGuid = { 0xEC87D643, 0xEBA4, 0x4BB5, { 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 }}
|
|
gWdtPersistentDataGuid = { 0x78ce2354, 0xcfbc, 0x4643, { 0xae, 0xba, 0x07, 0xa2, 0x7f, 0xa8, 0x92, 0xbf }}
|
|
gSetupDataHobGuid = { 0x822a9b23, 0x2386, 0x4377, { 0xb7, 0x05, 0x87, 0x78, 0xc1, 0xb8, 0xb3, 0x95 }}
|
|
gGpioDataBlockHobGuid = { 0x8FC7A6BE, 0x5DBE, 0x4800, { 0xB3, 0x5E, 0xCB, 0x4A, 0xD5, 0xAB, 0x01, 0x62 }}
|
|
# BpCommonPkg
|
|
gBiosIdGuid = { 0xC3E36D09, 0x8294, 0x4b97, { 0xA8, 0x57, 0xD5, 0x28, 0x8F, 0xE3, 0x3E, 0x28 } }
|
|
#[-start-200420-IB17800056-add]#
|
|
#
|
|
# ADL PO temporary add
|
|
#
|
|
## GUID to publish BIOS information HOB
|
|
gBiosInfoGuid = { 0x09d0d15c, 0xe9f0, 0x4dfc, {0x9e, 0x0b, 0x39, 0x33, 0x1f, 0xca, 0x66, 0x85} }
|
|
#[-end-200420-IB17800056-add]#
|
|
gEfiDefaultBmpLogoGuid = {0x7BB28B99, 0x61BB, 0x11d5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
|
|
gChipsetPkgTokenSpaceGuid = {0xffd4675e, 0xff47, 0x46d9, {0xac, 0x24, 0x8b, 0x33, 0x1f, 0x93, 0x77, 0x37}}
|
|
#
|
|
# Insyde Chipset Guids
|
|
#
|
|
gMtrrDataInfoGuid = {0x15c57af9, 0x1db3, 0x4cb7, {0x81, 0x2b, 0x71, 0xC2, 0x9B, 0xc3, 0x80, 0x37}}
|
|
## XtuInfoHod.h
|
|
gXTUInfoHobGuid = {0x8174b45b, 0x805e, 0x4682, {0x9d, 0x62, 0xae, 0x95, 0x9e, 0x82, 0xa2, 0x13}}
|
|
gOcSetupVariableGuid = {0x3524AF07, 0x4548, 0x7374, {0xC9, 0xCB, 0xA3, 0x92, 0xF2, 0x25, 0x12, 0x5D}}
|
|
gBiosGuardModuleGuid = {0x7934156d, 0xcfce, 0x460e, {0x92, 0xf5, 0xa0, 0x79, 0x09, 0xa5, 0x9e, 0xca}}
|
|
#
|
|
# Insyde Cpu Guids
|
|
#
|
|
#gTxtOneTouchGuid = {0x3D989471, 0xCFAC, 0x46B7, { 0x9B, 0x1C, 0x8, 0x43, 0x1, 0x9, 0x40, 0x2D }}
|
|
gTxtApStartupPeiFileGuid = {0xD1E59F50, 0xE8C3, 0x4545, { 0xBF, 0x61, 0x11, 0xF0, 0x02, 0x23, 0x3C, 0x97 }}
|
|
##
|
|
## TBT
|
|
##
|
|
gDTbtInfoHobGuid = {0xc2d628a1, 0xdd7a, 0x4865, {0xa8, 0xec, 0x89, 0x61, 0xf3, 0x57, 0xf8, 0x63}}
|
|
# BIOS ACM GUID. BIOS ACM interface is described in Intel Trusted Execution Technology BIOS Specification
|
|
# @pre BIOS ACM must be placed in flash part on 4KB boundary
|
|
gTxtBiosAcmPeiFileGuid = {0x2D27C618, 0x7DCD, 0x41F5, { 0xBB, 0x10, 0x21, 0x16, 0x6B, 0xE7, 0xE1, 0x43 }}
|
|
#
|
|
# Platform Guids
|
|
#
|
|
gH2OHybridGraphicsVariableGuid = { 0xb2b7c21f, 0x1786, 0x4a64, {0xbe, 0x69, 0x16, 0xce, 0xf7, 0x64, 0x73, 0x31 }}
|
|
gH2OHgInformationDataHobGuid = { 0x648ce07b, 0xae5d, 0x4973, {0xbd, 0x3c, 0x8c, 0x91, 0x53, 0xc0, 0x5d, 0xc5 }}
|
|
gPlatformBoardConfigPreMemGuid = { 0x44afdd70, 0xa7b1, 0x406f, {0x87, 0x8d, 0x8b, 0x4e, 0xb8, 0x1b, 0x57, 0xdf }}
|
|
gPlatformBoardConfigPostMemGuid = { 0x16eed7eb, 0x4b99, 0x4337, {0xe6, 0xa0, 0x21, 0x53, 0x56, 0x17, 0xcc, 0xe2 }}
|
|
# this GUID is the same as PTOpRom.bin
|
|
gEfiPerformanceFileGuid = {0x76824e51, 0x2fa9, 0x433e, {0x98, 0xf, 0xb7, 0x56, 0x70, 0xe7, 0xc5, 0xa7 }}
|
|
gEfiVbiosWaFileGuid = {0xD3033A61, 0x22AD, 0x4DD8, {0xBB, 0x1D, 0xA2, 0xED, 0xA0, 0xB1, 0xC1, 0x05}}
|
|
gVbtRvpFileGuid = {0x9F79F2C5, 0xCD1D, 0x4C02, {0xA2, 0x1B, 0x3E, 0x45, 0xF8, 0xC7, 0x70, 0x64}} # gChipsetPkgTokenSpaceGuid.PcdVbtRvpFile
|
|
gVbtRvp3Rvp7FileGuid = {0x878AC2CC, 0x5343, 0x46F2, {0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA}}
|
|
gVbtRvp10FileGuid = {0xde482306, 0x0f4e, 0x43bd, {0xb3, 0x2d, 0x79, 0x4c, 0x91, 0x4c, 0x02, 0x23}}
|
|
gVbtRvp11FileGuid = {0x134b46b0, 0xf5af, 0x4263, {0x97, 0x92, 0xc5, 0xe8, 0x8a, 0x4e, 0xfa, 0x02}}
|
|
gVbtRvp8FileGuid = {0xafcd4b58, 0xd4ba, 0x4388, {0x94, 0x44, 0x17, 0x42, 0xb9, 0x91, 0xb5, 0xc5}}
|
|
gGop1021VbtRvp3Rvp7FileGuid = {0x1d57d87, 0xd8ff, 0x4662, { 0xa8, 0xc2, 0x3e, 0xac, 0x91, 0xe9, 0x43, 0xdd}}
|
|
gGop1021VbtRvp10FileGuid = {0xa5a305e8, 0x1aa8, 0x4538, { 0x9b, 0x8, 0x31, 0xd1, 0x88, 0x47, 0xdf, 0xe6}}
|
|
gGop1021VbtRvp8FileGuid = {0x9f79f2c5, 0xcd1d, 0x4c02, { 0xa2, 0x1b, 0xe6, 0x5b, 0x6a, 0x59, 0x2b, 0x21}}
|
|
gCmosInVariableGuid = {0x6a0e13e9, 0x57d7, 0x4d5a, {0xbf, 0x7a, 0xdc, 0x0f, 0xda, 0xda, 0x25, 0xa7}}
|
|
gEfiSmmInt15ServiceProtocol2Guid = {0x316EE975, 0x902B, 0x4976, {0xA8, 0xC5, 0x36, 0x6E, 0xD2, 0x73, 0x69, 0x39}}
|
|
|
|
#
|
|
# eMMC
|
|
#
|
|
gScsEmmcSoftwareTuningVariableGuid = {0x565d7cc8, 0xadcb, 0x4ca3, {0x85, 0x74, 0x81, 0x6e, 0x01, 0x99, 0xd1, 0xef}}
|
|
|
|
#
|
|
# SEG Feature - Remove H2OUVE relevant source codes
|
|
#
|
|
# # Include/Guid/VariableEdit.h
|
|
gTbtInfoHobGuid = {0x74a81eaa, 0x033c, 0x4783, {0xbe, 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}}
|
|
gEfiTraceHubStatusCodeHandlePeiGuid = { 0x0fb3bcf9, 0x0a1d, 0x4598, { 0xa5, 0x21, 0xe5, 0xc8, 0x4e, 0x95, 0xd9, 0x7a } }
|
|
gEfiTraceHubStatusCodeHandleRuntimeDxeGuid = { 0xfcf51e6b, 0x527f, 0x438d, { 0xbe, 0x6d, 0xa6, 0xd1, 0x5f, 0x0c, 0xd9, 0x8b } }
|
|
gEfiTraceHubStatusCodeHandleSmmGuid = { 0xae0b5b70, 0xd044, 0x4456, {0xba, 0x51, 0x97, 0x0e, 0x4c, 0x68, 0x70, 0xbf}}
|
|
gEfiTraceHubTokenSpaceGuid = { 0xa69b58a9, 0x6c05, 0x4dc1, {0x85, 0xbf, 0xaf, 0x80, 0xdc, 0xe6, 0xd9, 0x7d}}
|
|
gEfiAcpiTableStorageGuid = { 0x7e374e25, 0x8e01, 0x4fee, {0x87, 0xf2, 0x39, 0x0c, 0x23, 0xc6, 0x06, 0xcd}}
|
|
gEfiTraceHubDebugLibIa32Guid = { 0x23a3e7ba, 0x75d1, 0x4cb9, {0x9c, 0x8f, 0x56, 0xfa, 0x4e, 0x48, 0xd9, 0x9e}}
|
|
gEfiTraceHubDebugLibX64Guid = { 0x8f7e1a3a, 0x9657, 0x44f0, {0xb9, 0xe6, 0x4e, 0xf7, 0x4b, 0x22, 0xd5, 0x43}}
|
|
gSaveUnLockedBarVariableGuid = { 0x39473DE5, 0xDF3B, 0x49A1, {0x9F, 0xA6, 0x41, 0xB3, 0x5B, 0x36, 0xFA, 0x39}}
|
|
gGpioCheckConflictHobGuid = {0x5603f872, 0xefac, 0x40ae, {0xb9, 0x7e, 0x13, 0xb2, 0xf8, 0x07, 0x80, 0x21}}
|
|
gUefiIntelCnvWlanVariablesGuid = {0x92daaf2f, 0xc02b, 0x455b, {0xb2, 0xec, 0xf5, 0xa3, 0x59, 0x4f, 0x4a, 0xea}}
|
|
gUefiIntelCnvBtVariablesGuid = {0x42780dd5, 0x9a7d, 0x404c, {0x80, 0xe4, 0x7f, 0x70, 0x94, 0x36, 0x03, 0x94}}
|
|
|
|
#
|
|
# Tbt Retimer Capsule Update Support Guids
|
|
#
|
|
gEfiTbtRetimerDevice0Guid = {0x86ca851c, 0x20ad, 0x4971, {0xa9, 0x1d, 0xb4, 0xee, 0xc6, 0xa7, 0x4d, 0x41}}
|
|
gEfiTbtRetimerDevice1Guid = {0xed3ca1b2, 0xdd7d, 0x40d4, {0xba, 0x5b, 0x75, 0xdf, 0xd9, 0x43, 0x39, 0x86}}
|
|
gEfiTbtRetimerDevice2Guid = {0x3a4f5c7c, 0x32bc, 0x4184, {0x93, 0xfa, 0x45, 0x48, 0x40, 0xed, 0x70, 0x24}}
|
|
gEfiTbtRetimerDevice3Guid = {0x726b9f37, 0x210f, 0x4839, {0xba, 0xfa, 0xcd, 0x99, 0x59, 0xca, 0xb3, 0xc2}}
|
|
gEfiTbtRetimerDevice4Guid = {0x44551ce4, 0x5b5f, 0x4bbd, {0xa3, 0x9e, 0x20, 0x90, 0xae, 0xad, 0xd3, 0x98}}
|
|
gEfiTbtRetimerDevice5Guid = {0xb1a6a8fb, 0x927b, 0x47a1, {0xb5, 0xf6, 0x70, 0xb8, 0xa8, 0x81, 0x85, 0x70}}
|
|
gEfiTbtRetimerDevice6Guid = {0x40366b75, 0x9196, 0x4e9c, {0xbb, 0x5f, 0xa3, 0x17, 0xd2, 0xca, 0xed, 0xe2}}
|
|
gEfiTbtRetimerDevice7Guid = {0x2945011e, 0xd33f, 0x4f23, {0xa8, 0x54, 0xc4, 0xc, 0x30, 0x15, 0x63, 0xfa}}
|
|
gEfiTbtRetimerDevice8Guid = {0x3c9c91eb, 0xe16a, 0x4877, {0x84, 0xa2, 0xaf, 0x53, 0x42, 0x33, 0x9f, 0x82}}
|
|
gEfiTbtRetimerDevice9Guid = {0x200c61c5, 0xfc1a, 0x4d60, {0x8b, 0xc9, 0xa8, 0x7e, 0xf9, 0xf3, 0xe8, 0x73}}
|
|
|
|
#
|
|
# Definition of Setup Token GUID for Formset List
|
|
#
|
|
#define FORMSET_ID_GUID_ADVANCE {0xc6d4769e, 0x7f48, 0x4d2a, 0x98, 0xe9, 0x87, 0xad, 0xcc, 0xf3, 0x5c, 0xcc}
|
|
#define FORMSET_ID_GUID_POWER {0xa6712873, 0x925f, 0x46c6, 0x90, 0xb4, 0xa4, 0x0f, 0x86, 0xa0, 0x91, 0x7b}
|
|
gIccGuid = {0x64192dca, 0xd034, 0x49d2, {0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74}}
|
|
# gEpcOsDataGuid = {0xd69a279b, 0x58eb, 0x45d1, {0xa1, 0x48, 0x77, 0x1b, 0xb9, 0xeb, 0x52, 0x51}}
|
|
# gEpcBiosDataGuid = {0xc60aa7f6, 0xe8d6, 0x4956, {0x8b, 0xa1, 0xfe, 0x26, 0x29, 0x8f, 0x5e, 0x87}}
|
|
gMeInfoSetupGuid = {0x78259433, 0x7b6d, 0x4db3, {0x9a, 0xe8, 0x36, 0xc4, 0xc2, 0xc3, 0xa1, 0x7d}}
|
|
gSinitSvnGuid = {0xacdc5eee, 0x9014, 0x4da4, {0x82, 0x0f, 0xd4, 0x3b, 0x78, 0x01, 0x0e, 0xc3}}
|
|
gSgxPolicyStatusGuid = {0x9cb2e73f, 0x7325, 0x40f4, {0xa4, 0x84, 0x65, 0x9b, 0xb3, 0x44, 0xc3, 0xcd}}
|
|
gChipsetSetupDafultGuid = { 0x16233F3E, 0xD2BF, 0x4DE4, {0x9b, 0x83, 0x3B, 0xB0, 0xA5, 0x81, 0xCA, 0x4D} }
|
|
## Include/IndustryStandard/Hsti.h
|
|
gAdapterInfoPlatformSecurityGuid = {0x6be272c7, 0x1320, 0x4ccd, { 0x90, 0x17, 0xd4, 0x61, 0x2c, 0x01, 0x2b, 0x25 }}
|
|
gChipsetCapsuleSignatureGuid = {0x4F2CDD19, 0xBA92, 0xD7E4, {0x14, 0x3F, 0x85, 0xD0, 0x3A, 0x5B, 0x1D, 0x6F}}
|
|
gIshUpdVerGuid = {0x5bdddc78, 0xd405, 0x48e0, {0xb0, 0x66, 0xef, 0x50, 0x02, 0x9d, 0xc4, 0x90}}
|
|
gPdtUpdCountGuid = {0x103fcd92, 0xa4e6, 0x4a07, {0xb4, 0x58, 0xf7, 0x8c, 0x9d, 0xb4, 0x52, 0x56}}
|
|
gTbtRetimer1VerGuid = {0x567ce681, 0x487d, 0x42ff, {0xb8, 0x75, 0x38, 0xc9, 0x63, 0xe5, 0xbb, 0x4c}}
|
|
gTbtRetimer2VerGuid = {0x125622a2, 0x2aeb, 0x4930, {0xa5, 0xa4, 0xe2, 0xb9, 0x95, 0x5b, 0x6d, 0x9e}}
|
|
gTbtRetimer3VerGuid = {0x95274f55, 0xf628, 0x4033, {0xa1, 0xe3, 0xe8, 0x8f, 0xb0, 0x8e, 0x04, 0x86}}
|
|
gTbtRetimer4VerGuid = {0xfd1a346e, 0x5fb3, 0x4122, {0x9f, 0x57, 0xe7, 0x10, 0x4b, 0x44, 0xa9, 0x49}}
|
|
gMeUpdCountGuid = {0x225722d1, 0x7d98, 0x4bca, {0x0b, 0x8e, 0x74, 0xc3, 0x17, 0x55, 0x07, 0x7f}}
|
|
gSecureEraseData = {0xA83D8873, 0x0A8C, 0x4FC3, {0x88, 0x61, 0x47, 0xA0, 0x4F, 0x54, 0xF3, 0x75}}
|
|
gPeiMCVarHookGuid = {0x61388566, 0xeb06, 0x465d, {0xbe, 0xf7, 0x10, 0x55, 0x6d, 0x70, 0x50, 0xc3}}
|
|
##
|
|
## HSTI
|
|
##
|
|
gPlatformConfigChangeGuid = {0xe3cacf62, 0x3062, 0x4e1d, {0x97, 0x8e, 0x46, 0x80, 0x7a, 0xb9, 0x74, 0x7d}}
|
|
#== Include/Guid/RcSetupUtility.h
|
|
gRcSetupUtilityVariableGuid = {0x6659b956, 0xcccb, 0x48aa, {0x92, 0x0b, 0xe6, 0x2f, 0x66, 0x7f, 0xf5, 0x78}}
|
|
#== Include/Guid/RcSetupUtility.h
|
|
gRcSetupUtilityBrowserVariableGuid = {0x3877eb12, 0x9286, 0x4e60, {0x82, 0xeb, 0x5a, 0x19, 0x29, 0x50, 0xfc, 0xee}}
|
|
#== Include/SetupVariable.h
|
|
gSaSetupVariableGuid = {0x72c5e28c, 0x7783, 0x43a1, {0x87, 0x67, 0xfa, 0xd7, 0x3f, 0xcc, 0xaf, 0xa4}}
|
|
#== Include/SetupVariable.h
|
|
gMeSetupVariableGuid = {0x5432122d, 0xd034, 0x49d2, {0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74}}
|
|
#== Include/SetupVariable.h
|
|
gCpuSetupVariableGuid = {0xb08f97ff, 0xe6e8, 0x4193, {0xa9, 0x97, 0x5e, 0x9e, 0x9b, 0xa, 0xdb, 0x32}}
|
|
gCpuSmmGuid = {0x90d93e09, 0x4e91, 0x4b3d, {0x8c, 0x77, 0xc8, 0x2f, 0xf1, 0xe, 0x3c, 0x81}}
|
|
#== Include/SetupVariable.h
|
|
gPchSetupVariableGuid = {0x4570b7f1, 0xade8, 0x4943, {0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84}}
|
|
gSiSetupVariableGuid = {0xAAF8E719, 0x48F8, 0x4099, {0xA6, 0xF7, 0x64, 0x5F, 0xBD, 0x69, 0x4C, 0x3D}}
|
|
#== Include/SetupVariable.h
|
|
gMeSetupStorageVariableGuid = {0xa41e9236, 0x4d21, 0x43b5, {0x93, 0x79, 0xdd, 0xd6, 0xfa, 0xfe, 0x66, 0x03}}
|
|
#gFspWrapperReservedMemoryResourceHobGuid = {0x52f5fa83, 0xa4aa, 0x4b71, {0x91, 0x5e, 0x7e, 0x4, 0x13, 0x69, 0x65, 0x53}}
|
|
gFspHobGuid = {0x6d86fb36, 0xba90, 0x472c, {0xb5, 0x83, 0x3f, 0xbe, 0xd3, 0xfb, 0x20, 0x9a}}
|
|
gFspApiPerformanceGuid = {0xc9122295, 0x56ed, 0x4d4e, {0x06, 0xa6, 0x50, 0x8d, 0x89, 0x4d, 0x3e, 0x40}}
|
|
gH2OFlashMapRegionPeiFv0Guid = {0x7d5fdcf6, 0xacb0, 0x4b7b, {0xbd, 0x93, 0xab, 0x59, 0x83, 0x0f, 0x81, 0xb5}}
|
|
gHstiSmmVariableGuid = {0xb8a9de42, 0xdc5b, 0x4529, {0x8c, 0x6a, 0x8d, 0x89, 0x45, 0x5b, 0x4f, 0x6e}}
|
|
|
|
#
|
|
# GUID defined in PI1.4
|
|
#
|
|
## Include/Guid/GraphicsInfoHob.h
|
|
gEfiGraphicsInfoHobGuid = { 0x39f62cce, 0x6825, 0x4669, { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 }}
|
|
|
|
##
|
|
## AcpiTables
|
|
##
|
|
gGRAcpiTableStorageGuid = { 0x43e33fbc, 0xdbdc, 0x44e5, { 0x8e, 0x68, 0x02, 0x13, 0xd9, 0xec, 0x72, 0xca }}
|
|
gSdsAcpiTableStorageGuid = { 0x4f996d3a, 0x6bbf, 0x4078, { 0xa4, 0x9c, 0xaf, 0x24, 0x1b, 0x75, 0x4e, 0x32 }}
|
|
gOcAcpiTableStorageGuid = { 0x22D85435, 0xF24A, 0x43DB, { 0x7D, 0x04, 0x01, 0x56, 0x06, 0xDF, 0x21, 0xB1 }}
|
|
gDptfAcpiTableStorageGuid = { 0xea139578, 0xfea0, 0x4dd2, {0x91, 0xb5, 0x69, 0x53, 0x81, 0x9e, 0xf1, 0xe4 }}
|
|
gDptfAcpiTableStorageGuidHsbSds = { 0x2820908b, 0x87f6, 0x446b, { 0xa1, 0x0, 0x74, 0xee, 0xe3, 0x6e, 0x29, 0x18 } }
|
|
gDptfAcpiTableStorageGuidSds = { 0x3bbb09da, 0x1e0f, 0x469b, { 0x89, 0x97, 0xd4, 0x40, 0xf1, 0x1, 0xd6, 0xf1 } }
|
|
gDptfAcpiTableStorageGuidLlama = { 0x4b57ca25, 0x395f, 0x4e31, { 0xb2, 0xe4, 0x67, 0x72, 0x2, 0x6, 0x18, 0xd4 }}
|
|
|
|
## Include/MultiPlatSupport.h
|
|
gDefaultDataFileGuid = {0x1ae42876, 0x008f, 0x4161, {0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43}}
|
|
gDefaultDataOptSizeFileGuid = {0x003e7b41, 0x98a2, 0x4be2, {0xb2, 0x7a, 0x6c, 0x30, 0xc7, 0x65, 0x52, 0x25}}
|
|
|
|
#
|
|
# FileGuids of FMP device driver (ImageTypeId)
|
|
#
|
|
gFmpDevicePlatformMonolithicGuid = {0x7FEB1D5D, 0x33F4, 0x48D3, {0xBD, 0x11, 0xC4, 0xB3, 0x6B, 0x6D, 0x0E, 0x57}}
|
|
# gFmpDevicePlatformBiosGuid = {0x6C8E136F, 0xD3E6, 0x4131, {0xAC, 0x32, 0x46, 0x87, 0xCB, 0x4A, 0xBD, 0x27}}
|
|
|
|
gDebugConfigVariableGuid = {0xDE0A5E74, 0x4E3E, 0x3D96, {0xA4, 0x40, 0x2C, 0x96, 0xEC, 0xBD, 0x3C, 0x97}}
|
|
gDebugConfigHobGuid = {0x2f6a6bb7, 0x9dc7, 0x4bf6, {0x94, 0x04, 0x22, 0x70, 0xc0, 0xe3, 0xbe, 0x2f}}
|
|
gChassisIntrudeDetHobGuid = {0xdea43de2, 0x756b, 0x4b3b, {0x75, 0x1c, 0xad, 0xeb, 0x8d, 0xff, 0x56, 0xa3}}
|
|
|
|
# AsfSecureBootVariable.h
|
|
gAsfSecureBootVariableGuid = { 0x14B6D115, 0x657C, 0x4CC5, { 0xA7, 0xA3, 0xA7, 0x97, 0x55, 0x41, 0x5B, 0x63 }}
|
|
gCrashLogDataBufferHobGuid = {0xf3c1138e, 0xcd89, 0x4e20, {0x9e, 0x68, 0x25, 0xa6, 0x76, 0x95, 0xa5, 0x6b}}
|
|
gSgxSetupVariableGuid = {0x45b5acb9, 0x0359, 0x49be, {0xad, 0xb1, 0x49, 0x37, 0x7b, 0xd6, 0x07, 0xf7} }
|
|
|
|
##
|
|
## NhltTable
|
|
##
|
|
gHdaExternalNhltTableGuid = {0x06adc9b7, 0x837f, 0x47df, {0xac, 0x0c, 0xa0, 0xee, 0x18, 0xbf, 0xad, 0x67}}
|
|
gElixirSpringsPatchGuid = {0x6bf7a32b, 0xefd9, 0x44b0, { 0xb1, 0x1c, 0xa7, 0x4f, 0x4, 0x47, 0xdf, 0x82}}
|
|
gSkipBiosLockForSysFwUpdateGuid = {0x922b911b, 0x4dbb, 0x4b02, {0xbf, 0xfa, 0x46, 0xe7, 0x97, 0xb0, 0x45, 0x07}}
|
|
# Hob and Variable guid specify System firmware update progress.
|
|
gSysFwUpdateDigiestGuid = {0x5060073d, 0x88c3, 0x421f, {0x82, 0xf8, 0x28, 0x3f, 0x0d, 0x29, 0xed, 0x90}}
|
|
gFmpCapsuleInfoGuid = {0x718fd53c, 0xea37, 0x4305, {0x91, 0x87, 0x94, 0x55, 0x22, 0x7c, 0x24, 0x1e}}
|
|
gBiosInfoFlagGuid = {0x5dbaccb0, 0x62cf, 0x4a53, {0x89, 0x9b, 0x28, 0x37, 0x41, 0xa8, 0x68, 0x9e}}
|
|
|
|
|
|
gPlatformOsDnxEventGuid = {0x5e84f15a, 0xea7f, 0x47fe, {0x84, 0x44, 0x5f, 0xeb, 0x2c, 0xf4, 0x12, 0x9f}}
|
|
# H2OChipsetCp.h ChipSet Check Point
|
|
gH2OPeiCpEcSendSetBssbConnected = {0x00fdc16f, 0x53a3, 0x4cf5, {0xac, 0x2e, 0x42, 0x1c, 0xd3, 0xd9, 0xee, 0x49}}
|
|
gH2ODxeCpEcGetSendGetUsciVerGuid = {0xfd4d4681, 0xf8c2, 0x4af2, {0x88, 0xe9, 0x89, 0x52, 0xe6, 0x78, 0xbc, 0x5b}}
|
|
gH2OSmmCpEcSendEspiClearGuid = {0x88b6a6d0, 0x073e, 0x428e, {0xad, 0xb5, 0x17, 0x12, 0x99, 0x14, 0x92, 0x24}}
|
|
gH2OPeiCpBiosGuardEcSupportGuid = {0xddacac79, 0x8748, 0x4c9e, {0x9b, 0x86, 0x08, 0x02, 0xb3, 0x86, 0x0e, 0xb3}}
|
|
gH2OPeiCpBiosGuardUpdateBgpdtGuid = {0x0505a75b, 0xd952, 0x494b, {0x86, 0xbc, 0xa1 ,0x34, 0xaf, 0x87, 0x5c, 0x9e}}
|
|
gFvBinariesFileGuid = {0x1186FD18, 0x89D3, 0x43BF, {0x9D, 0x69, 0x38, 0x55, 0x10, 0x04, 0x0E, 0x26}}
|
|
#
|
|
# BoardPkg.dec
|
|
#
|
|
gEfiSmbiosVariableGuid = {0xeada2a50, 0x9daa, 0x4303, {0xba, 0x0e, 0xe0, 0xf5, 0xb3, 0x2a, 0x88, 0xb5}}
|
|
gSetupNvramUpdateGuid = {0xd84beff0, 0x159a, 0x4b60, {0x9a, 0xb9, 0xac, 0x5c, 0x47, 0x4b, 0xd3, 0xb1}}
|
|
gBootDeviceInfoGuid = {0x5BD6B672, 0xB6EA, 0x4D6A, {0xB5, 0x90, 0x18, 0xA9, 0x32, 0xB7, 0x87, 0x94}}
|
|
#
|
|
# MinPlatformPkg.dec
|
|
#
|
|
gMinPlatformPkgTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
|
|
# Include/Guid/WifiConnectionManagerConfigHii.h
|
|
gFwRecovery2FvGuid = {0x8579D1CA, 0x45E8, 0x4f1c, {0xA7, 0x89, 0xFF, 0xA7, 0x70, 0x67, 0x20, 0x99}}
|
|
|
|
gFwBinaryFvGuid = {0x7bbb3e42, 0x5a6a, 0x4080, {0x80, 0x77, 0xcf, 0x05, 0xe6, 0xcf, 0x8d, 0x2c}}
|
|
gSbbDigestGuid = {0xB2DA2CA8, 0x7259, 0x4F79, {0x64, 0xA4, 0xF7, 0x12, 0x62, 0x5E, 0xD2, 0xC9}}
|
|
gArbSvnInfoGuid = {0x643d5856, 0xc4f9, 0x4abe, {0x9c, 0x27, 0x33, 0x1a, 0xe3, 0x66, 0x39, 0xaa}}
|
|
gArbSvnInfoHobGuid = {0xa7b2f845, 0x1519, 0x4932, {0x83, 0x28, 0xb7, 0x93, 0x9f, 0xd0, 0x3d, 0x6a}}
|
|
gChasmfallsCrisisRecoveryGuid = {0xb036610c, 0x6a5c, 0x43c3, {0x91, 0xc1, 0x75, 0x69, 0x84, 0xd4, 0x71, 0xde}}
|
|
gChasmfallsTopSwapStatusGuid = {0x0cc43ca0, 0x4f5a, 0x442d, {0xa6, 0xbf, 0xd0, 0x2b, 0xe8, 0x26, 0x59, 0xa8}}
|
|
|
|
[Ppis]
|
|
#
|
|
# Insyde Chipset Ppis
|
|
#
|
|
gPlatformStage1PeiPpiGuid = {0x1051cae0, 0xd9a7, 0x4fa6, {0x85, 0xf8, 0xaa, 0x4a, 0xc4, 0x54, 0x99, 0xfa}}
|
|
#
|
|
# Insyde Cpu Ppis
|
|
#
|
|
gPeiOverClockPpiGuid = {0xd80544af, 0xe8b5, 0x4bcc, {0xa8, 0x0a, 0xc7, 0x21, 0x45, 0xa9, 0x6a, 0x80}}
|
|
#
|
|
# Insyde Platform Ppis
|
|
#
|
|
## Include/Ppi/HybridGraphics.h
|
|
#[-start-190613-IB16990067-add]#
|
|
gHybridGraphicsReadyForPowerSequenceInit = {0xb2fda03a, 0xec47, 0x4b22, {0xb7, 0xdd, 0xf1, 0x2f, 0x51, 0x4f, 0x4d, 0xc3}}
|
|
#[-end-190613-IB16990067-add]#
|
|
gH2OHybridGraphicsPpiGuid = {0x8daf8e3d, 0xf580, 0x4b2e, {0xa7, 0xbe, 0xc4, 0xfa, 0xe5, 0x42, 0xab, 0x8e}}
|
|
gEfiTraceHubStatusCodeHandlePpi = { 0x882c5d54, 0x1dad, 0x4f4a, { 0x83, 0x16, 0x4b, 0xdf, 0x84, 0x1e, 0x9, 0xd0 } }
|
|
gEfiTraceHubStatusCodeHandleHeaderPpi = { 0x787e0c4a, 0x4a27, 0x4891, { 0x94, 0x89, 0xaf, 0x50, 0x74, 0xc3, 0x6e, 0x89 } }
|
|
gPlatformBoardConfigPreMemPpiGuid = {0xad8dd79e, 0xef24, 0x4997, {0x80, 0x88, 0xd5, 0xd2, 0x59, 0x48, 0x10, 0x28}}
|
|
gPlatformBoardConfigPostMemPpiGuid = {0x1cacaf7d, 0xcd53, 0x4050, {0x06, 0xad, 0x2f, 0xf9, 0xeb, 0xf7, 0x7e, 0xc5}}
|
|
|
|
gPatchConfigurationDataPreMemPpiGuid = {0xa09b1a0c, 0x690c, 0x4d48, {0xa8, 0x98, 0xa1, 0x2c, 0x94, 0x26, 0xd7, 0x06}}
|
|
##
|
|
## TBT
|
|
##
|
|
gPeiDTbtPolicyPpiGuid = {0xbec8b921, 0xb70b, 0x4041, {0x92, 0xc1, 0x37, 0x24, 0xdb, 0xad, 0x72, 0x64}}
|
|
## Include/Ppi/NvmExpressController.h
|
|
gPeiNvmExpressControllerPpiGuid = {0x580366f1, 0x399b, 0x482a, {0x8b, 0x4f, 0xb2, 0x74, 0x4a, 0xa9, 0x20, 0x04}}
|
|
## Include/Ppi/NvmExpressPassThru.h
|
|
gPeiNvmExpressPassThruPpiGuid = {0xba45de19, 0x9220, 0x4349, {0xbf, 0xed, 0x68, 0xf3, 0x89, 0x2c, 0x12, 0x9c}}
|
|
gPeiBoardConfigInitDonePpiGuid = {0x794cc0b1, 0x3e8b, 0x4cc6, {0x90, 0x2a, 0x07, 0x62, 0xaa, 0x13, 0xb2, 0x25}}
|
|
|
|
## Include/Ppi/MultiBoardDetected.h
|
|
gPeiCustomerMultiBoardDetectedPpiGuid = { 0x48c935ea, 0xc017, 0x440d, { 0x96, 0x75, 0xbe, 0x13, 0xaf, 0x82, 0xf1, 0x12 } }
|
|
|
|
[Protocols]
|
|
gEmmcDriverStrengthProtocolGuid = {0xb004564a, 0x2f63, 0x44f4, {0x96, 0x15, 0xbf, 0x0c, 0xcd, 0x20, 0x9d, 0xd8}}
|
|
gDxePolicyProtocolGuid = {0xd5e1268b, 0xf62b, 0x4b12, {0xbb, 0x27, 0xcb, 0xf0, 0x7a, 0xe7, 0xb8, 0xb9}}
|
|
#
|
|
# Insyde Chipset Protocols
|
|
#
|
|
gConOutDevStartedProtocolGuid = {0xef9a3971, 0xc1a0, 0x4a93, {0xbd, 0x40, 0x5a, 0xa1, 0x65, 0xf2, 0xdc, 0x3a}}
|
|
gEfiProgramSsidSvidProtocolGuid = {0x67BA958, 0x7D99, 0x461D, {0x9D, 0xC, 0x8C, 0x55, 0x74, 0xA9, 0x83, 0x5B}}
|
|
gSpttDataProtocolGuid = {0xef791955, 0xf629, 0x49c5, {0xab, 0x38, 0x98, 0xc3, 0x6b, 0x83, 0xba, 0x64}}
|
|
gEfiEcAccessProtocolGuid = {0x70eeecbe, 0x727a, 0x4244, {0x90, 0x4c, 0xdb, 0x6b, 0xf0, 0x05, 0x53, 0x92}}
|
|
gEfiPlatformInfoProtocolGuid = {0x97069458, 0xd915, 0x468c, {0xa7, 0x9b, 0xa1, 0x28, 0x46, 0xf7, 0x4a, 0x19}}
|
|
gH2OHybridGraphicsEventProtocolGuid = { 0xa9647a1c, 0x1814, 0x44d0, {0x8e, 0x75, 0x59, 0xa8, 0x26, 0xb2, 0x33, 0xe6} }
|
|
gH2OHybridGraphicsInfoProtocolGuid = { 0x4d96c24c, 0xcb7, 0x4650, {0x91, 0x7c, 0x3b, 0xb, 0x70, 0xa6, 0x7f, 0xba} }
|
|
gEfiHybridGraphicsProtocolGuid = { 0xa9647a1c, 0x1814, 0x44d0, {0x8e, 0x75, 0x59, 0xa8, 0x26, 0xb2, 0x33, 0xe6} }
|
|
gSpttTableServicesProtocolGuid = {0x40918dc6, 0xde56, 0x4ed1, {0x86, 0xd5, 0x60, 0xdb, 0xf2, 0x58, 0xa4, 0x77}}
|
|
gEfiI2cHcAccessProtocolGuid = { 0x5beccc5a, 0x19c9, 0x42eb, {0x8e, 0x44, 0x9c, 0xb3, 0x97, 0x74, 0x85, 0xe8} }
|
|
gEfiI2cPlatformSpecificProtocolGuid = { 0xC4700DAB, 0x41B6, 0x4FDF, {0xBA, 0xF2, 0xFF, 0x36, 0x97, 0xE3, 0xAA, 0xCC} }
|
|
gEfiRamDiskDummyProtocolGuid = { 0xdf6fb9bc, 0x2671, 0x4682, {0xb4, 0x0f, 0x99, 0x3a, 0x18, 0xc0, 0xb3, 0xc8} }
|
|
gInternalFlashBiosProtocolGuid = { 0x8E033BB2, 0x8F00, 0x4DF6, { 0x8B, 0x21, 0x48, 0x10, 0xEC, 0x73, 0xBA, 0x72 }}
|
|
#[-start-190709-16990077-add]#
|
|
gH2OMeStatusProtocolGuid = { 0x89e70ece, 0x1d19, 0x455d, { 0x97, 0x3f, 0x6d, 0x13, 0xe9, 0x7c, 0xe8, 0x92 }}
|
|
#[-end-190709-16990077-add]#
|
|
#
|
|
# Insyde Cpu Protocols
|
|
#
|
|
#
|
|
# Insyde Platform Protocol
|
|
#
|
|
# gPlatformNvsAreaProtocolGuid = {0x074e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc}}
|
|
gEfiPciHostBridgeEndResourceAllocationNotifyGuid = {0xBA2E7D85, 0xF570, 0x0361, {0x82, 0x2E, 0x26, 0x5D, 0xFD, 0xB7, 0xCF, 0x01}}
|
|
gEfiSmmSmbusProtocolGuid = {0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc }}
|
|
gDxePlatformXtuPolicyGuid = {0x565245c9, 0x9eb7, 0x468e, {0xbd, 0x51, 0x00, 0x85, 0x7c, 0x45, 0x35, 0x96}}
|
|
gGopDisplayBrightnessProtocoGuid = {0x6FF23F1D, 0x877C, 0x4B1B, {0x93, 0xFC, 0xF1, 0x42, 0xB2, 0xEE, 0xA6, 0xA7}}
|
|
gEfiHgNvsAreaProtocolGuid = {0xbb210948, 0x3101, 0x4cef, {0x8d, 0x1d, 0x3f, 0xe5, 0x5e, 0x61, 0x53, 0xb4}}
|
|
gSmmThunkProtocolGuid = {0x2a82fce6, 0x8bb6, 0x413e, { 0xb9, 0xeb, 0x45, 0xdf, 0xc0, 0x52, 0x2d, 0xf3 }}
|
|
gEfiSmmLockEnablePointProtocolGuid = {0x402522C1, 0x6264, 0x456F, { 0x8D, 0x79, 0xE7, 0x81, 0x04, 0x62, 0x00, 0x6A }}
|
|
#
|
|
# SEG Feature - Remove H2OUVE relevant source codes
|
|
#
|
|
gEfiInstallExitPmAuthAndEndOfDxeProtocolGuid = {0xD218864D, 0x3BC3, 0x49A8, {0x95, 0x78, 0x76, 0x10, 0x3B, 0x2E, 0xB6, 0x09}}
|
|
#
|
|
# OSReset SMM Protocol
|
|
#
|
|
gEfiOSResetPolicyProtocolGuid = {0x7bcb9b1a, 0x72f1, 0x4f25, {0xac, 0x36, 0xa9, 0x54, 0x80, 0x5d, 0x40, 0xb7}}
|
|
gEfiChangeVbiosBootDisplayProtocolGuid = {0x2876CB69, 0xF5E2, 0x41BF, {0xB1, 0x69, 0x0C, 0xF0, 0xDD, 0xE5, 0x66, 0x8B}}
|
|
#
|
|
# IntelFrameworkPkg
|
|
#
|
|
gSaveUnlockedBarDoneProtocolGuid = { 0x41aaad7f, 0x6edd, 0x4924, {0xbb, 0x0b, 0xc3, 0xd6, 0xcc, 0xd8, 0xac, 0x46}}
|
|
gDxeDisableDTbtBmeProtocolGuid = { 0x29627704, 0xf178, 0x442c, {0x8e, 0x1b, 0xfc, 0x29, 0x94, 0x3a, 0x46, 0x59}}
|
|
gDxeDTbtPolicyProtocolGuid = { 0x714aedbd, 0xfbf6, 0x4cf9, {0xb5, 0xc7, 0xb9, 0x3a, 0xbd, 0x21, 0xe0, 0xcd}}
|
|
gAmtWrapperProtocolGuid = { 0x919383de, 0xebac, 0x4924, {0x01, 0x94, 0x52, 0x59, 0xe0, 0x0d, 0x65, 0x7a}}
|
|
gCrisisGopGuid = { 0x8691bb99, 0x4bfa, 0x4beb, {0x81, 0x07, 0xa8, 0x14, 0x5b, 0x39, 0x06, 0xa0}}
|
|
gGopGuid = { 0xf831fc3e, 0x9a5c, 0x45bc, {0x9a, 0x52, 0x8a, 0x1f, 0x2c, 0x10, 0x1c, 0x64}}
|
|
#== Include/Guid/PlatformInfoProtocol.h
|
|
gAddPerfRecordProtocolGuid = { 0xc4a58d6d, 0x3677, 0x49cb, {0xa0, 0x0a, 0x94, 0x70, 0x76, 0x5f, 0xb5, 0x5e}}
|
|
gOverClockProtocolGuid = { 0xacb2de3e, 0x0955, 0x42a7, {0xb0, 0x31, 0x47, 0x96, 0xcb, 0x3e, 0xd6, 0x2d}}
|
|
gPlatformConfigChangeProtocolGuid = { 0xf429c00a, 0x9640, 0x46b3, {0x95, 0x44, 0xf8, 0xf8, 0x6a, 0x28, 0xf3, 0x0f}}
|
|
##
|
|
## AcpiTables
|
|
##
|
|
gDTbtNvsAreaProtocolGuid = {0xd7778b4c, 0x85b5, 0x479b, {0xa8, 0x83, 0x80, 0xbd, 0x23, 0xeb, 0x1c, 0x48}}
|
|
|
|
gEfiCnvUefiVariablesProtocolGuid = {0xc77ae557, 0x40a3, 0x41c0, {0xac, 0xe6, 0x71, 0x43, 0x8c, 0x60, 0xf8, 0x71}}
|
|
|
|
gEfiTbtRetimerProtocolGuid = {0xB9AC2BD1, 0xD450, 0x4BEC, {0xBD, 0x5B, 0x19, 0x26, 0x1, 0x11, 0x9B, 0x84}}
|
|
#
|
|
# RST protocols
|
|
#
|
|
gRstLegacyBootDisabledProtocolGuid = {0x5b10cdc8, 0x5733, 0x4c4c, {0x89, 0xd5, 0x59, 0xd9, 0xfe, 0xd, 0x5c, 0x91}}
|
|
#
|
|
# BoardPkg.dec
|
|
#
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gPeiAtaHostControllerPpiGuid = {0xb659e3f2, 0xd5ab, 0x4bfb, {0x90, 0x42, 0xff, 0x52, 0x86, 0x83, 0x41, 0xf1}}
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gPeiAtaPassThruPpiGuid = {0xa0e44ace, 0x9777, 0x4598, {0x9a, 0xfe, 0x28, 0x8a, 0x83, 0xf4, 0xda, 0x96}}
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gTDSBlockConInProtocolGuid = {0xBB03FDA0, 0xEA70, 0x423C, {0x86, 0xCB, 0x69, 0xE6, 0xF6, 0x6B, 0x3C, 0x3E}}
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gChasmfallsConnectAllStorageGuid = {0xd60820c4, 0x1ad2, 0x4837, {0x96, 0x8a, 0x57, 0xdd, 0xbb, 0x4e, 0x15, 0x42}}
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[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
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