148 lines
5.7 KiB
Plaintext
148 lines
5.7 KiB
Plaintext
/** @file
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;******************************************************************************
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;* Copyright (c) 2018 - 2021, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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#ifndef _AMD_ULT_POWERXPRESS_ASI_
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#define _AMD_ULT_POWERXPRESS_ASI_
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//
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// ASL code common define about device and bridge
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//
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#define PCI_SCOPE \_SB.PC00
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#define DGPU_BRIDGE_SCOPE PCI_SCOPE.RP08
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#define DGPU_DEVICE PXSX
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#define DGPU_AUDIO_DEVICE PEGA
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#define DGPU_SCOPE DGPU_BRIDGE_SCOPE.DGPU_DEVICE
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#define DGPU_AUDIO_SCOPE DGPU_BRIDGE_SCOPE.DGPU_AUDIO_DEVICE
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#define IGPU_SCOPE PCI_SCOPE.GFX0
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#define EC_SCOPE PCI_SCOPE.LPCB.H_EC
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//
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// ATI GFX Interface function define
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//
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#define ATIF_VERIFY_INTERFACE 0
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#define ATIF_GET_SYSTEM_PARAMETERS 1
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#define ATIF_GET_SBIOS_REQUESTS 2
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#define ATIF_SELECT_ACTIVE_DISPLAY 3
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#define ATIF_READY_TO_UNDOCK 17
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#define ATIF_DISABLE_OS_GPU_HOTPLUG 18
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#define ATIF_RETRIEVE_DGPU_PCI_CFG 19
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#define ATIF_GET_TB_DEVICE_INFO 20
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#define ATIF_GET_DGPU_INFO 21
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//
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// ATI PowerXpress function define
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//
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#define PX_VERIFY_POWERXPRESS_INTERFACE 0x0
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#define PX_GET_POWERXPRESS_PARAMETERS 0x1
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#define PX_POWER_CONTROL 0x2
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#define PX_DISPLAY_MULTIPLEXER_CONTROL 0x3
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#define PX_MONITOR_I2C_CONTROL 0x4
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#define PX_GFX_SWITCH_START_NOTIFICATION 0x5
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#define PX_GFX_SWITCH_END_NOTIFICATION 0x6
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#define PX_GET_DISPLAY_CONNECTORS_MAPPING 0x8
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//
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// The display combinations in the list...
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// bit0: LCD1, bit1: CRT1, bit2: TV1, bit3: DFP1, bit7: DFP2
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// Bit9: DFP3, Bit10: DFP4, Bit11: DFP5
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//
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// 1 - LCD1 (LCD)
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#define TOGGLE_LIST_ENTRIES_LCD1 0x0002
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// 2 - CRT1 (CRT)
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#define TOGGLE_LIST_ENTRIES_CRT1 0x0001
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// 3 - DFP1 (DVI)
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#define TOGGLE_LIST_ENTRIES_DFP1 0x0008
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// 4 - DFP2 (HDMI)
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#define TOGGLE_LIST_ENTRIES_DFP2 0x0080
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// 5 - DFP3
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#define TOGGLE_LIST_ENTRIES_DFP3 0x0200
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// 6 - DFP4
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#define TOGGLE_LIST_ENTRIES_DFP4 0x0400
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// 7 - DFP5
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#define TOGGLE_LIST_ENTRIES_DFP5 0x0800
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// 8 - CRT1 + LCD1
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#define TOGGLE_LIST_ENTRIES_CRT1_LCD1 0x0003
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// 9 - CRT1 + DFP1
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#define TOGGLE_LIST_ENTRIES_CRT1_DFP1 0x0009
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// 10 - CRT1 + DFP2
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#define TOGGLE_LIST_ENTRIES_CRT1_DFP2 0x0081
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// 11 - CRT1 + DFP3
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#define TOGGLE_LIST_ENTRIES_CRT1_DFP3 0x0201
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// 12 - CRT1 + DFP4
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#define TOGGLE_LIST_ENTRIES_CRT1_DFP4 0x0401
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// 13 - CRT1 + DFP5
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#define TOGGLE_LIST_ENTRIES_CRT1_DFP5 0x0801
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// 14 - NULL
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#define TOGGLE_LIST_ENTRIES_NULL 0x0000
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// Total number of toggle list entries
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#define TOGGLE_LIST_ENTRIES_NUMBER 15
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#define TOGGLE_LIST_ENTRIES_01 TOGGLE_LIST_ENTRIES_LCD1
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#define TOGGLE_LIST_ENTRIES_02 TOGGLE_LIST_ENTRIES_CRT1
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#define TOGGLE_LIST_ENTRIES_03 TOGGLE_LIST_ENTRIES_DFP1
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#define TOGGLE_LIST_ENTRIES_04 TOGGLE_LIST_ENTRIES_DFP2
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#define TOGGLE_LIST_ENTRIES_05 TOGGLE_LIST_ENTRIES_DFP3
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#define TOGGLE_LIST_ENTRIES_06 TOGGLE_LIST_ENTRIES_DFP4
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#define TOGGLE_LIST_ENTRIES_07 TOGGLE_LIST_ENTRIES_DFP5
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#define TOGGLE_LIST_ENTRIES_08 TOGGLE_LIST_ENTRIES_CRT1_LCD1
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#define TOGGLE_LIST_ENTRIES_09 TOGGLE_LIST_ENTRIES_CRT1_DFP1
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#define TOGGLE_LIST_ENTRIES_10 TOGGLE_LIST_ENTRIES_CRT1_DFP2
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#define TOGGLE_LIST_ENTRIES_11 TOGGLE_LIST_ENTRIES_CRT1_DFP3
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#define TOGGLE_LIST_ENTRIES_12 TOGGLE_LIST_ENTRIES_CRT1_DFP4
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#define TOGGLE_LIST_ENTRIES_13 TOGGLE_LIST_ENTRIES_CRT1_DFP5
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#define TOGGLE_LIST_ENTRIES_14 TOGGLE_LIST_ENTRIES_NULL
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#define TOGGLE_LIST_ENTRIES_15 TOGGLE_LIST_ENTRIES_NULL
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//
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// You need to set this when on an AMD Muxed project. The "Port Type" table is shown below,
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// and it should be set by project. It is used by IGPU_SCOPE.ATPX function 8.
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//
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// HG MUX DID format
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// MUX: 1 = iGPU Only, 2 = dGPU Only, 3 = Shared
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// <HPD MUX> <Aux MUX> <Display MUX> <Port Type>
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// Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0
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//
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// <Port ID> <Port Type>
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// 0x0 Reserved
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// 0x1 Analog VGA
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// 0x2 LVDS
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// 0x3 Reserved
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// 0x4 HDMI/DVI_B
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// 0x5 HDMI/DVI_C
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// 0x6 HDMI/DVI_D
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// 0x7 DisplayPort_A
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// 0x8 DisplayPort_B
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// 0x9 DisplayPort_C
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// 0xA DisplayPort_D
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// 0x0E INTEL Wireless Display
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//
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// CRT
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#define SG_MUX_DID_1 0x00030301
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// eDP
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#define SG_MUX_DID_2 0x00030307
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// DisplayPort_B
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#define SG_MUX_DID_3 0x03030308
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// HDMI_B
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#define SG_MUX_DID_4 0x03030304
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// HDMI_C
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#define SG_MUX_DID_5 0x03030305
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// DisplayPort_D
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#define SG_MUX_DID_6 0x0303030A
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// HDMI_D
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#define SG_MUX_DID_7 0x03030306
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// LFP
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#define SG_MUX_DID_8 0x00030302
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// Unused
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#define SG_MUX_DID_9 0x00000000
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#endif
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