607 lines
21 KiB
Plaintext
607 lines
21 KiB
Plaintext
/** @file
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;******************************************************************************
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;* Copyright (c) 2019, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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Scope (DGPU_BRIDGE_SCOPE)
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{
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OperationRegion (RPCX, SystemMemory, PCI_SCOPE.DGBA, 0x1000) // Bridge
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Field (RPCX, DWordAcc, NoLock, Preserve)
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{
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Offset (0x04), // Command Register
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CMDR, 8,
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Offset (0x4A), // Device Status Register
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CEDR, 1,
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Offset (0x69), // Device Control2 Register
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, 2,
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LREN, 1,
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Offset (0xA4),
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D0ST, 2,
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}
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}
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Scope (DGPU_SCOPE)
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{
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OperationRegion (PCNV, SystemMemory, PCI_SCOPE.DGDA, 0x1000) // dGPU
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Field (PCNV, DWordAcc, NoLock, Preserve)
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{
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Offset (0x4),
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CMDR, 8,
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VGAR, 2008,
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Offset (0x488),
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, 25,
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HDAE, 1, // HDA Multifunction bit Register
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}
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OperationRegion (DGPU, SystemMemory, PCI_SCOPE.DGDA, 0x100)
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Field (DGPU, DWordAcc, NoLock, Preserve)
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{
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Offset (0x40), // Offset (64)
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SSSV, 32
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}
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// OperationRegion (PCAP, PCI_Config, EECP, 0x14)
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// Field (PCAP, DWordAcc, NoLock, Preserve)
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// {
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// Offset (0xC), // Offset (12),
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// , 4,
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// EMLW, 6,
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// Offset (0x10), // Offset (16),
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// LCTL, 16
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// }
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Name (VGAB, Buffer(0xFB)
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{
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0x00
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})
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Name (LTRE, Zero) // Buffer for LTR Save/Restore
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Method (_STA, 0, Serialized)
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{
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Return (0x0F) // For Optimus function, always return DGPU is powered-ON
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}
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Method (_PS0, 0x0)
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{
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If (LNotEqual (DGPS, Zero))
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{
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PCI_SCOPE.HGON (Zero) // IBV_customize: call to dGPU ON method
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If (LNotEqual (GPRF, One))
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{
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Store (VGAB, VGAR)
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}
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Or (And (PCI_SCOPE.ELCT, 0x43), And (PCI_SCOPE.LCTR, 0xFFBC), PCI_SCOPE.LCTR)
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Store (Zero, DGPS)
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Store (Zero, HDAE) // Disable dGPU HDA device in _PS0 anyway
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}
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}
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Method (_PS3, 0x0)
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{
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If (LEqual (OMPR, 0x3))
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{
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Store (PCI_SCOPE.LCTR, PCI_SCOPE.ELCT)
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If (LNotEqual (GPRF, One))
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{
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Store (VGAR, VGAB)
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}
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PCI_SCOPE.HGOF (Zero) // IBV_customize: call to dGPU OFF method
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Store (One, DGPS)
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Store (0x2, OMPR)
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}
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}
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Method (GOBT, 1)
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{
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Name (OPVK, Buffer()
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{
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// Key below is *NOT A REAL KEY*, it is for reference
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// Customer need to ask NVIDIA PM to get the key
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// Customer need to put the key in between labels "// key start -" and
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// "// key end -". Please consult NVIDIA PM if any issues
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// Key start -
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00
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// Key end -
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})
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CreateWordField (Arg0, 2, USRG) // Object type signature passed in by driver.
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If (LEqual (USRG, 0x564B)) {
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Return (OPVK) // 'VK' for Optimus Validation Key Object.
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}
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Return (Zero)
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}
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Name (DGPS, Zero) // DGPU Power Status 0:on 1:off
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Name (OMPR, 0x2) // Optimus MXM Power-Control Ready
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Name (DPST, One)
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Name (GPRF, Zero)
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Method (NVOP, 4, Serialized) // Called from Method (_DSM)
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{
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// Only Interface Revision 0x0100 is supported
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If (LNotEqual (Arg1, 0x100))
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{
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Return (STATUS_ERROR_UNSPECIFIED)
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}
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// (Arg2) Sub-Function
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Switch (ToInteger (Arg2))
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{
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//
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// Function 0: NVOP_FUNC_SUPPORT - Bit list of supported functions.
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//
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case (NVOP_FUNC_SUPPORT)
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{
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/*
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Store (Buffer(4) {0, 0, 0, 0}, Local0)
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Divide (NVOP_FUNC_SUPPORT, 8, Local2, Local1) // Function 0
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// Local1 is Quotient, Local2 is Remainder
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ShiftLeft (0x01, Local2, Local2)
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Or (DeRefOf (Index (Local0, Local1)), Local2, Index (Local0, Local1))
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Divide (NVOP_FUNC_OPTIMUSCAPS, 8, Local2, Local1) // Function 0x1A
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ShiftLeft (0x01, Local2, Local2)
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Or (DeRefOf (Index (Local0, Local1)), Local2, Index (Local0, Local1))
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// force IGPU
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Divide (NVOP_FUNC_OPTIMUSFLAGS, 8, Local2, Local1) // Function 0x1B
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ShiftLeft (0x01, Local2, Local2)
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Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1))
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// Force IGPU
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Divide (NVOP_FUNC_GETOBJBYTYPE, 8, Local2, Local1) // Function 0x10
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ShiftLeft (0x01, Local2, Local2)
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Or (DeRefOf (Index(Local0, Local1)), Local2, Index (Local0, Local1))
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Divide (NVOP_FUNC_MDTL, 8, Local2, Local1) // Function 0x06
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ShiftLeft(0x01, Local2, Local2)
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Or (DeRefOf (Index (Local0, Local1)), Local2, Index (Local0, Local1))
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Divide (NVOP_FUNC_DISPLAYSTATUS, 8, Local2, Local1) // Function 0x05
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ShiftLeft (0x01, Local2, Local2)
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Or (DeRefOf (Index (Local0, Local1)), Local2, Index (Local0, Local1))
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Return (Local0)
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*/
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Return (Buffer(0x04)
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{
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// sub-func: 0, 5, 6, 16, 26, 27 supported
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0x61, 0x00, 0x01, 0x0C
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})
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}
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//
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// Function 5: NVOP_FUNC_DISPLAYSTATUS - Query the Display Hot-Key.
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//
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case (NVOP_FUNC_DISPLAYSTATUS)
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{
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CreateField (Arg3, 31, 1, NCSM) // Check the next combination sequence mask bit 31.
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Store (0, Local0)
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If (LEqual (ToInteger (NCSM), 0x1))
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{
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CreateField (Arg3, 25, 5,NCIN) // Get the next combination sequence number bit 29:25
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Store (ToInteger (NCIN), DPST) // Store the current valid value from driver
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Add (DPST, 1, DPST) // Add 1 to it because SBIOS needs to give the next combination sequence
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Mod (DPST, 18, Local0)
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}
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Else
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{
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If (LEqual (DPST, 0x0))
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{
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// SBIOS sequence number should not return index 0
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Add (DPST, 1, DPST)
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}
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// Just for testing, display status is implemented without the logic of attach and active display
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Mod (DPST, 18, Local0)
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ShiftLeft (Local0, 0x8, Local0) // Shift left 8 bits because display status is between bit 8:13
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Add (DPST, 1, DPST)
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}
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Return (Local0)
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}
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//
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// Function 6: NVOP_FUNC_MDTL - Query Display Toggle List.
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//
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case (NVOP_FUNC_MDTL)
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{
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// Display Toggle List
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Name (TMP6, Package()
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{
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ones, 0x2C, // LVDS
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ones, 0x2C, // CRT
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ones, 0x2C, // HDMI
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ones, ones, 0x2C, // LVDS + CRT
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ones, ones, 0x2C, // LVDS + HDMI
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ones, ones, 0x2C // CRT + HDMI
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})
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// Update Display Toggle List
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Store (DID2, Index (TMP6, 0)) // LVDS
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Store (DID1, Index (TMP6, 2)) // CRT
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Store (DID4, Index (TMP6, 4)) // HDMI
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Store (DID2, Index (TMP6, 6)) // LVDS + CRT
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Store (DID1, Index (TMP6, 7))
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Store (DID2, Index (TMP6, 9)) // LVDS + HDMI
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Store (DID4, Index (TMP6, 10))
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Store (DID1, Index (TMP6, 12)) // CRT + HDMI
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Store (DID4, Index (TMP6, 13))
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Return (TMP6)
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}
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//
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// Function 16: NVOP_FUNC_GETOBJBYTYPE - Get Data Object.
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//
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case (NVOP_FUNC_GETOBJBYTYPE)
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{
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Return (DGPU_SCOPE.GOBT (Arg3))
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}
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//
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// Function 26: NVOP_FUNC_OPTIMUSCAPS - Optimus Capabilities.
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//
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case (NVOP_FUNC_OPTIMUSCAPS)
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{
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CreateField (Arg3, 0, 1, FLCH)
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CreateField (Arg3, 1, 1, DVSR) // Modify Optimus DSM 0x1A for GC6 TDR support.
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CreateField (Arg3, 2, 1, DVSC) // Modify Optimus DSM 0x1A for GC6 TDR support.
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CreateField (Arg3, 24, 2, OPCE)
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If (LAnd (ToInteger (FLCH), LNotEqual (ToInteger (OPCE), OMPR)))
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{
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Store (ToInteger (OPCE), OMPR) // Optimus Power Control Enable - From DD
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}
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// Definition of return buffer.
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// bit 0 - Optimus Enabled
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// 0 : Optimus Graphics Disabled
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// 1 : Optimus Graphics Enabled (default)
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// bit 4:3 - Current GPU Control Status
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// 0 : GPU is powered off
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// 3 : GPU power has stabilized (default)
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// bit 6 - Shared discrete GPU Hot-Plug Capabilities
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// 1 : There are discrete GPU Display Hot-Plug signals co-connected to the platform
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// bit 8 - PCIe Configuration Space Owner Actual
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// 0 : SBIOS
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// 1 : GPU Driver
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// bit 26:24 - Optimus Capabilities
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// 0 : No special platform capabilities
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// 1 : Platform has dynamic GPU power control
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// bit 27:28 - Optimus HD Audio Codec Capabilities
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// 0 : No audio codec-related capabilities
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// 1 : Platform does not use HD audio
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// 2 : Platform supports Optimus dynamic codec control
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Store (Buffer(4) {0, 0, 0, 0}, Local0)
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CreateField (Local0, 0, 1, OPEN)
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CreateField (Local0, 3, 2, CGCS)
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CreateField (Local0, 6, 1, SHPC) // Shared discrete GPU Hot-Plug Capabilities
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CreateField (Local0, 8, 1, SNSR) // Modify Optimus DSM 0x1A for GC6 TDR support.
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CreateField (Local0, 24, 3, DGPC) // Optimus Power Capabilities
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CreateField (Local0, 27, 2, OHAC) // Optimus HD Audio Codec Capabilities
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Store (One, OPEN) // Optimus Enabled
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Store (One, SHPC) // Set '1' indicates there are discrete GPU Display Hot-Plug signals co-connected to the platform
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Store (One, DGPC) // Optimus Power Capabilities
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// 0: No special platform capabilities
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// 1: Dynamic GPU Power Control
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Store (0x2, OHAC) // Optimus HD Audio Codec Capabilities
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// 0: No audio codec-related capabilities
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// 1: Platform does not use HD audio (SBIOS will always disable audio codecs)
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// 2: Optimus dynamic codec control
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// 3: Dynamic power state reporting
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If (ToInteger (DVSC))
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{
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If (ToInteger (DVSR))
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{
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Store (One, GPRF)
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}
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Else
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{
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Store (Zero, GPRF)
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}
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}
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Store (GPRF, SNSR)
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If (LEqual (DGPS, Zero)) // IBV_customize: root port path
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{
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Store (0x3, CGCS) // Current GPU Control status: On
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}
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Else
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{
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Store (0x0, CGCS) // Current GPU Control status: Off
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}
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Return (Local0)
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}
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//
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// Function 27: NVOP_FUNC_OPTIMUSFLAGS - Optimus State flags.
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//
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case (NVOP_FUNC_OPTIMUSFLAGS)
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{
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Store (Arg3, Local0)
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CreateField (Local0, 0, 1, OPFL)
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CreateField (Local0, 1, 1, OPVL)
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If (ToInteger (OPVL))
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{
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Store (Zero, OPTF)
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If (ToInteger (OPFL))
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{
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Store(One, OPTF)
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}
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}
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Store (OPTF, Local0)
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Return (Local0)
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}
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default
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{
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//
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// FunctionCode or SubFunctionCode not supported
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//
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Return (STATUS_ERROR_UNSUPPORTED)
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}
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}
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}
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//
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// dGPU just output to HDMI in Optimus HW artchetecture
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//
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Method (_DOD, 0, NotSerialized)
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{
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Return (Package(0x01) {ACPI_ID_HDMI})
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}
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// method : _ROM
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// Arguments:
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// Arg0: Integer Offset of the graphics device ROM data
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// Arg1: Integer Size of the buffer to fill in (up to 4K)
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//
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// Return Value:
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// Returns Buffer Buffer of requested video ROM bytes
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Method (_ROM, 2)
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{
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Store (Arg0, Local0)
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Store (Arg1, Local1)
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Name (VROM, Buffer(Local1) {0x00}) // Create 4K buffer to return to DD
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If (LGreater (Local1, 0x1000))
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{
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Store (0x1000, Local1) // Return dummy buffer if asking for more than 4K
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}
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If (LGreater (Arg0, RVBS))
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{
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Return (VROM) // Return dummy buffer if asking beyond VBIOS image
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}
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Add (Arg0, Arg1, Local2)
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If (LGreater (Local2, RVBS)) // If requested BASE+LEN > VBIOS image size
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{
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Subtract (RVBS, Local0, Local1) // Limit length to the final chunk of VBIOS image
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}
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Divide (Local0, 0x8000, Local3, Local4) // (Dividend, Divisor, Remainder, Result)
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Switch (Local4)
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{
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Case (0)
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{
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Store (DGPU_SCOPE.VBS1, Local5)
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}
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Case (1)
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{
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Store (DGPU_SCOPE.VBS2, Local5)
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}
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Case (2)
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{
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Store (DGPU_SCOPE.VBS3, Local5)
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}
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Case (3)
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{
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Store (DGPU_SCOPE.VBS4, Local5)
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}
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Case (4)
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{
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Store (DGPU_SCOPE.VBS5, Local5)
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}
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Case (5)
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{
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Store (DGPU_SCOPE.VBS6, Local5)
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}
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Case (6)
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{
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Store (DGPU_SCOPE.VBS7, Local5)
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}
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Case (7)
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{
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Store (DGPU_SCOPE.VBS8, Local5)
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}
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}
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Multiply (0x8000, Local4, Local4) // (Multiplicand, Multiplier, Result)
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Subtract (Local0, Local4, Local0)
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Mid (Local5, Local0, Local1, VROM)
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Return (VROM)
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}
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Method (MXMX, 1, Serialized)
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{
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If (LEqual (Arg0, Zero))
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{
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// Acquire DDC/AUX mux
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// No mutex implemented. No need to acquire mutex.
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// Set mux to dGPU
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P8XH (One, 0x99)
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P8XH (Zero, Zero)
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Return (One)
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}
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If (LEqual (Arg0, One))
|
|
{
|
|
// Release DDC/AUX mux
|
|
// No mutex implemented. No need to release mutex.
|
|
// 2-way mux. Hence no need to do anything
|
|
P8XH (One, 0x99)
|
|
P8XH (Zero, one)
|
|
|
|
Return (One)
|
|
}
|
|
If (LEqual (Arg0, 0x02))
|
|
{
|
|
P8XH (One, 0x99)
|
|
P8XH (Zero, 0x02)
|
|
|
|
// Get ddc/aux mux status for dGPU
|
|
}
|
|
|
|
Return (Zero)
|
|
}
|
|
|
|
Method (MXDS, 1, Serialized)
|
|
{
|
|
If (LEqual (Arg0, Zero))
|
|
{
|
|
// Get display mux status for dGPU
|
|
}
|
|
If (LEqual (Arg0, One))
|
|
{
|
|
// Set display mux to dGPU
|
|
}
|
|
Return (Zero)
|
|
}
|
|
|
|
Method (_DSM, 4, SERIALIZED)
|
|
{
|
|
//
|
|
// Check for Nvidia Optimus _DSM UUID
|
|
//
|
|
// NVOP_DSM_GUID {A486D8F8-0BDA-471B-A72B-6042A6B5BEE0}
|
|
If (LEqual (Arg0, ToUUID ("A486D8F8-0BDA-471B-A72B-6042A6B5BEE0")))
|
|
{
|
|
Return (DGPU_SCOPE.NVOP (Arg0, Arg1, Arg2, Arg3))
|
|
}
|
|
|
|
//
|
|
// Check for Nvidia GPS _DSM UUID
|
|
//
|
|
// GPS_DSM_GUID {A3132D01-8CDA-49BA-A52E-BC9D46DF6B81}
|
|
If (LEqual (Arg0, ToUUID ("A3132D01-8CDA-49BA-A52E-BC9D46DF6B81")))
|
|
{
|
|
If (LNotEqual (DGPU_SCOPE.GPSS, Zero))
|
|
{
|
|
Return (DGPU_SCOPE.GPS (Arg0, Arg1, Arg2, Arg3))
|
|
}
|
|
}
|
|
|
|
//
|
|
// Check for Nvidia Optimus GC6 _DSM UUID
|
|
//
|
|
// GC6_DSM_GUID {CBECA351-067B-4924-9CBD-B46B00B86F34}
|
|
If (LEqual (Arg0, ToUUID ("CBECA351-067B-4924-9CBD-B46B00B86F34")))
|
|
{
|
|
If (LNotEqual (DGPU_SCOPE.GC6S, Zero))
|
|
{
|
|
Return (DGPU_SCOPE.NVJT (Arg0, Arg1, Arg2, Arg3))
|
|
}
|
|
}
|
|
|
|
//
|
|
// Check for Nvidia NBCI _DSM UUID
|
|
//
|
|
// NBCI_DSM_GUID {D4A50B75-65C7-46F7-BFB7-41514CEA0244}
|
|
If (LEqual (Arg0, ToUUID ("D4A50B75-65C7-46F7-BFB7-41514CEA0244")))
|
|
{
|
|
If (LNotEqual (DGPU_SCOPE.NBCS, Zero))
|
|
{
|
|
Return (DGPU_SCOPE.NBCI (Arg0, Arg1, Arg2, Arg3))
|
|
}
|
|
}
|
|
|
|
//
|
|
// Check for Nvidia SPB _DSM UUID
|
|
//
|
|
// SPB_DSM_GUID {95DB88FD-940A-4253-A446-70CE0504AEDF}
|
|
If (LEqual (Arg0, ToUUID ("95DB88FD-940A-4253-A446-70CE0504AEDF")))
|
|
{
|
|
If (LNotEqual (DGPU_SCOPE.VENS, Zero))
|
|
{
|
|
Return (IGPU_SCOPE.SPB (Arg0, Arg1, Arg2, Arg3))
|
|
}
|
|
}
|
|
|
|
If (LEqual (Arg0, ToUUID ("4004A400-917D-4cf2-B89C-79B62FD55665")))
|
|
{
|
|
Switch (ToInteger (Arg2))
|
|
{
|
|
//
|
|
// Function 0: MXM_FUNC_MXSS
|
|
//
|
|
case (MXM_FUNC_MXSS)
|
|
{
|
|
// Sub-Functions 0,16,24 are supported
|
|
Return (ToBuffer (0x01010001))
|
|
}
|
|
|
|
//
|
|
// Function 24: MXM_FUNC_MXMI
|
|
//
|
|
case (MXM_FUNC_MXMI)
|
|
{
|
|
Return (ToBuffer (0x30))
|
|
}
|
|
|
|
//
|
|
// Function 16: MXM_FUNC_MXMS
|
|
//
|
|
case (MXM_FUNC_MXMS)
|
|
{
|
|
If(LEqual (Arg1, 0x300))
|
|
{
|
|
If (LNotEqual (MXBS, 0))
|
|
{
|
|
Name (MXM3, Buffer(MXBS) {0x00})
|
|
Store (MXMB, MXM3)
|
|
Return (MXM3)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
Return (STATUS_ERROR_UNSUPPORTED) // MXM_ERROR_UNSUPPORTED - FunctionCode or SubfunctionCode not supported
|
|
}
|
|
Return (STATUS_ERROR_UNSPECIFIED) // MXM_ERROR_UNSPECIFIED
|
|
}
|
|
}
|