154 lines
4.3 KiB
Plaintext
154 lines
4.3 KiB
Plaintext
/** @file
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;******************************************************************************
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;* Copyright (c) 2020 - 2021, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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/*
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== Readme ==
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For NVIDIA general support, SBIOS has to set below GPIO config:
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- Please search keyword: IBV_customize and OEM_customize to match platform design
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*/
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Scope (DGPU_BRIDGE_SCOPE)
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{
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OperationRegion (RPCX, SystemMemory, PCI_SCOPE.DGBA, 0x1000) // PEG Root Port.
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Field (RPCX, DWordAcc, NoLock, Preserve)
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{
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Offset (0x04),
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CMDR, 8, // Command Register
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Offset (0x19),
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PRBN, 8, // Primary Bus Number
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Offset (0x4A), // Device Status Register
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CEDR, 1,
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Offset (0x69), // Device Control2 Register
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, 2,
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LREN, 1,
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Offset (0xA4),
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D0ST, 2,
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}
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/* GSTA: Get dGPU Power state
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* Arguments: (0)
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* None
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*
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* Return: Zero: Current Power state is OFF
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* One: Current Power state is ON
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*
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* Note: OEM_customize need to add PWR_OK pin GPIO number for "PWOK".
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* Or figure out different approach to get dGPU power state,
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* like PXE_RST pin (PWR_EN does not recommend due to GC6 no control it).
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*/
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Method (GSTA, 0, NotSerialized)
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{
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If(LEqual(\_SB.GGIV(DGPU_SCOPE.PWGD), Zero)) //OEM_customize
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{
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Return (Zero) // retrun dGPU Off
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}
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Else
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{
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Return (One) // retrun dGPU On
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}
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}
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}
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Scope (DGPU_SCOPE)
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{
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Name (LTRE, Zero) // Buffer for LTR Save/Restore
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Method (_STA, 0)
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{
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Return (0x0F)
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}
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OperationRegion (PCIM, SystemMemory, PCI_SCOPE.DGDA, 0x1000) // dGPU
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Field (PCIM, DWordAcc, NoLock, Preserve)
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{
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NVID, 16,
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NDID, 16,
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CMDR, 8,
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VGAR, 2008,
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Offset (0x48B),
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, 1,
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HDAE, 1
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}
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OperationRegion (DGPU, SystemMemory, PCI_SCOPE.DGDA, 0x100) // dGPU
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Field (DGPU, DWordAcc, NoLock, Preserve)
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{
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Offset (0x40), // Offset(64)
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SSSV, 32
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}
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Method (_DSM, 4, Serialized)
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{
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//
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// Check for Nvidia Optimus _DSM UUID
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//
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// NVOP_DSM_GUID {A486D8F8-0BDA-471B-A72B-6042A6B5BEE0}
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If (LEqual (Arg0, ToUUID ("A486D8F8-0BDA-471B-A72B-6042A6B5BEE0")))
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{
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Return (DGPU_SCOPE.NVOP (Arg0, Arg1, Arg2, Arg3))
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}
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//
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// Check for Nvidia GPS _DSM UUID
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//
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// GPS_DSM_GUID {A3132D01-8CDA-49BA-A52E-BC9D46DF6B81}
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If (LEqual (Arg0, ToUUID ("A3132D01-8CDA-49BA-A52E-BC9D46DF6B81")))
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{
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If (LNotEqual (DGPU_SCOPE.GPSS, Zero))
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{
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Return (DGPU_SCOPE.GPS (Arg0, Arg1, Arg2, Arg3))
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}
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}
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//
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// Check for Nvidia GC6 _DSM UUID
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//
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// GC6_DSM_GUID {CBECA351-067B-4924-9CBD-B46B00B86F34}
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If (LEqual (Arg0, ToUUID ("CBECA351-067B-4924-9CBD-B46B00B86F34")))
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{
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If (LNotEqual (DGPU_SCOPE.GC6S, Zero))
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{
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Return (DGPU_SCOPE.NVJT (Arg0, Arg1, Arg2, Arg3))
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}
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}
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//
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// Check for Nvidia NBCI _DSM UUID
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//
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// NBCI_DSM_GUID {D4A50B75-65C7-46F7-BFB7-41514CEA0244}
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If (LEqual (Arg0, ToUUID ("D4A50B75-65C7-46F7-BFB7-41514CEA0244")))
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{
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If (LNotEqual (DGPU_SCOPE.NBCS, Zero))
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{
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Return (DGPU_SCOPE.NBCI (Arg0, Arg1, Arg2, Arg3))
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}
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}
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//
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// Check for MXM _DSM UUID
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//
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//[-start-210917-GEORGE0004-modify]//
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//[-start-210918-QINGLIN0068-modify]//
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//#ifndef S77014_SUPPORT
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#if !defined(S77014_SUPPORT) && !defined(S570_SUPPORT) && !defined(S77014IAH_SUPPORT)
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//[-end-210918-QINGLIN0068-modify]//
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If (LEqual (Arg0, ToUUID ("4004A400-917D-4cf2-B89C-79B62FD55665")))
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{
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Return (DGPU_SCOPE.MXM (Arg0, Arg1, Arg2, Arg3))
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}
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#endif
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//[-end-210917-GEORGE0004-modify]//
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Return (STATUS_ERROR_UNSPECIFIED)
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}
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} |