116 lines
3.5 KiB
C
116 lines
3.5 KiB
C
/** @file
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;******************************************************************************
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;* Copyright (c) 2017 - 2021, Insyde Software Corp. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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#ifndef _CHIPSET_SMI_TABLE_DEFINE_H_
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#define _CHIPSET_SMI_TABLE_DEFINE_H_
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typedef enum {
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//
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// Kernel must use 0x01~0x4F as SW_SMI command number. Register on SmiTable.h
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//
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//
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// OEM must use 0xc0~0xDF as SW_SMI command number. Register on OemSwSmi.h
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//
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//
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// 0xE0 reserved for ODM Usage
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//
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INT15_HOOK = 0x15,
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//
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// Write PDR Command
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//
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Write_PDR_SW_SMI = 0x51,
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//
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// Initial Cipher for S3
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//
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Re_Init_Cipher = 0x52,
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Return_PDR0_Data = 0x53,
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SMMBASE_SW_SMI = 0x55,
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ASF_SECURE_BOOT_SMI = 0x56,
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//
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EFI_PEP_BCCD_SW_SMI = 0x58,
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// XTU SMI
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//
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EFI_PERF_TUNE_SW_SMI = 0x72,
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INT10_HOOK_FOR_INTEL_VBIOS = 0x74,
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//
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// Nvidia Optimus _ON/_OFF save/restore SMI
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//
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OPTIMUS_SAVE_PEG_REGISTER = 0x7A,
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OPTIMUS_RESTORE_PEG_REGISTER = 0x7B,
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OPTIMUS_SET_DISPLAY_MODE = 0x7C,
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//
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// OS_COMMAND
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//
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PPM_OS_COMMAND = 0x80,
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//
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// INIT_COMMAND
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//
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PPM_INIT_COMMAND = 0x81, //no function
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//
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// APP_COMMAND
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//
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PPM_APP_COMMAND = 0x82,
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//
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// OS_REQUEST
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//
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PPM_OS_REQUEST = 0x83, //no function
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//
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// CSTATE_COMMAND
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//
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PPM_CSTATE_COMMAND = 0x85, //no function
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//
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// IST_INIT_OS_TRANSITION
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//
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PPM_IST_INIT_OS_TRANSITION = 0x86,
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//
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// SEG Feature - Remove H2OUVE relevant source codes
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//
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// //
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// // For Variable Editor Tool
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// //
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// IVE_SW_SMI = 0x97,
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PPM_INTERNAL_SW_SMI = 0xE4,
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S3_RESTORE_MSR_SW_SMI = 0xE5,
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POWER_STATE_SWITCH_SMI = 0xE6,
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ENABLE_C_STATE_IO_REDIRECTION_SMI = 0xE7,
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DISABLE_C_STATE_IO_REDIRECTION_SMI = 0xE8,
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ENABLE_P_STATE_HARDWARE_COORDINATION_SMI = 0xE9,
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DISABLE_P_STATE_HARDWARE_COORDINATION_SMI = 0xEA,
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BIOS_LOCK_SW_SMI = 0xEB,
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//
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// Thunderbolt SMI Handler
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//
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THUNDERBOLT_SW_SMI = 0xF1,
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AMT_FLASH_SW_SMI = 0xF2,
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AMT_FLASH_WRITE_PROTECT_POST_COMPLETE_SW_SMI = 0xF3,
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//
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// Smm platform
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//
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PCIE_HOT_PLUG_SMI = 0xF4,
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ME_LOCK_SW_SMI = 0xF5,
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I_TBT_ENUMRATE = 0xF6, //Reserved for PcdSwSmiITbtEnumerate
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D_TBT_ENUMRATE = 0xF7 //Reserved for PcdSwSmiDTbtEnumerate
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}CHIPSET_SW_SMI_PORT_TABLE;
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#endif
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