449 lines
18 KiB
C
449 lines
18 KiB
C
/** @file
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;******************************************************************************
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;* Copyright (c) 2020, Insyde Software Corporation. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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/** @file
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Definitions for HECI driver
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2006 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#ifndef _SMM_HECI_LIB_H
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#define _SMM_HECI_LIB_H
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#include <CoreBiosMsg.h>
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#include <Register/MeRegs.h>
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/**
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Abstract ME BIOS Boot Path definitions.
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BIOS Boot Path vs. MEI1 Host Firmware Status 1, 4, and 5 registers:
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MeNormalBiosPath -
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If (HECI_FWS_REGISTER.r.CurrentState == ME_STATE_NORMAL AND
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HECI_FWS_REGISTER.r.ErrorCode == ME_ERROR_CODE_NO_ERROR)
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- BIOS takes the normal firmware BIOS path.
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MeErrorWithoutDidMsgBiosPath -
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If HECI_FWS_REGISTER.r.ErrorCode == ME_ERROR_CODE_IMAGE_FAILURE
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- The BIOS does not send any Intel MEI messages including DID and EOP message.
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- The BIOS does not invoke the Intel MEBX and should hide Intel MEBX hotkey entry.
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- MEI 1 device should be enabled by the BIOS so it allows the user to update the new firmware and
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take the firmware out of a recovery or error condition. Hide MEI 2, MEI3, SOL and IDER. In addition,
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Image Failure results in a platform involuntary 30-minute shut down triggered by Intel ME.
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BIOS shall post the warning message as part of the error handling flow.
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MeErrorBiosPath -
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If (HECI_FWS_REGISTER.r.FptBad == 0x01) OR
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(HECI_FWS_REGISTER.r.ErrorCode != ME_ERROR_CODE_NO_ERROR) OR
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(HECI_FWS_REGISTER.r.ErrorCode != ME_ERROR_CODE_IMAGE_FAILURE)
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- The BIOS does not send any Intel MEI messages except for the DRAM Init Done message. Moreover,
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the BIOS doesn't even send EOP message.
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- The BIOS does not invoke the Intel MEBX and should hide Intel MEBX hotkey entry.
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- MEI 1 device should be enabled by the BIOS so it allows the user to update the new firmware and
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take the firmware out of a recovery or error condition. Hide MEI 2, SOL and IDER.
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MeRecoveryBiosPath -
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If HECI_FWS_REGISTER.r.CurrentState == ME_STATE_RECOVERY
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- The BIOS does not send any Intel MEI messages except for MEI Bus and MKHI messages, MKHI MCA Group is not allowed.
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- The BIOS does not invoke the Intel MEBX and should hide Intel MEBX hotkey entry.
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- MEI 1 device should be enabled by the BIOS so it allows the user to update the new firmware and
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take the firmware out of a recovery or error condition. Hide MEI 2, SOL and IDER.
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MeDebugModeBiosPath -
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If HECI_FWS_REGISTER.r.MeOperationMode == ME_OPERATION_MODE_DEBUG
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- The BIOS does not send any Intel MEI messages except for DID and EOP message.
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- The BIOS does not invoke the Intel MEBX and should hide Intel MEBX hotkey entry.
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- Hide MEI1, MEI2, MEI3, SOL and IDER before OS boot. It means there is no MEI drivers loaded in OS environment.
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MeEnhancedDebugModeBiosPath -
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If HECI_FWS_REGISTER.r.MeOperationMode == ME_OPERATION_MODE_ENHANCED_DEBUG
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- Allowed messages: IMR / DID / SET_EDEBUG_STATE_CMD / READ_FROM_MPHY
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- The BIOS does not invoke the Intel MEBX and should hide Intel MEBX hotkey entry.
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- Hide MEI1, MEI2, MEI3, SOL and IDER before OS boot. It means there is no MEI drivers loaded in OS environment.
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MeSwTempDisableBiosPath
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If (HECI_FWS_REGISTER.r.MeOperationMode == ME_OPERATION_MODE_SOFT_TEMP_DISABLE)
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- The BIOS does not send any Intel MEI messages except for the DRAM Init Done message, Set Me Enable message
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and Global Reset Message.
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Moreover, the BIOS doesn't even send EOP message.
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- The BIOS does not invoke the Intel MEBX and should hide Intel MEBX hotkey entry.
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- Hide MEI2, MEI3, SOL and IDER before OS boot. It means there is no MEI drivers loaded in OS environment.
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Hides MEI1 device after sending the Set Me Enable message or prior to boot.
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It means there is no MEI drivers loaded in OS environment.
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MeSecoverJmprBiosPath
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If (HECI_FWS_REGISTER.r.MeOperationMode == ME_OPERATION_MODE_SECOVR_JMPR)
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- The BIOS does not send any Intel MEI messages except for the DRAM Init Done message. Moreover,
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the BIOS doesn't even send EOP message.
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- The BIOS does not invoke the Intel MEBX and should hide Intel MEBX hotkey entry.
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- Hide MEI1, MEI2, MEI3, SOL and IDER before OS boot. It means there is no MEI drivers loaded in OS environment.
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MeSecoverMeiMsgBiosPath
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If HECI_FWS_REGISTER.r.MeOperationMode == ME_OPERATION_MODE_SECOVR_HECI_MSG
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- The BIOS does not send any Intel MEI messages except for the DRAM Init Done (DID) message and HMRFPO DISABLE message.
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The HMRFPO DISABLE message is to bring the firmware out of SECOVR_MEI_MSG operation mode back to normal.
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- The BIOS does not invoke the Intel MEBX and should hide Intel MEBX hotkey entry.
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- Hide MEI2, MEI3, SOL and IDER before OS boot.
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Hides MEI1 device after sending the HMRFPO DISABLE message.
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It means there is no MEI drivers loaded in OS environment.
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MeEnforcementWithoutDidMsgBiosPath
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If HECI_FW_STS4_REGISTER.r.FwInEnfFlow == 1
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- The BIOS does not send any Intel MEI messages including DID and EOP message.
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- The BIOS does not invoke the Intel MEBX and should hide Intel MEBX hotkey entry.
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- Hide MEI1, MEI2, MEI3, SOL and IDER before OS boot.
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**/
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/**
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The FW registers may report multiple status to reflect Me Bios boot path, BIOS will follow the
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prioritized Me Bios boot path to continue boot. If the priority will be changed, then
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BOOT_PATH enumeration shall be adjusted as well to reflect real priority.
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**/
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typedef enum {
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NormalPath = 0,
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ErrorPath,
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RecoveryPath,
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ErrorWithoutDidMsgPath,
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SecoverMeiMsgPath,
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SwTempDisablePath,
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SecoverJmprPath,
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DebugModePath,
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EnhancedDebugModePath,
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EnforcementWithoutDidMsgPath,
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SpsPath,
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SpsRcvPath,
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MaxPathValue
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} ME_BIOS_BOOT_PATH;
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/**
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Abstract devices map for CSME devices to be hidden
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Bit0 - MEI1
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Bit1 - MEI2
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Bit2 - MEI3
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Bit3 - MEI4
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Bit7 - SOL
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**/
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typedef UINT8 ME_DEV_EXPOSURE;
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#define HIDE_MEI1 BIT0
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#define HIDE_MEI2 BIT1
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#define HIDE_MEI3 BIT2
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#define HIDE_MEI4 BIT3
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#define HIDE_SOL BIT7
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#define HIDE_AMT_DEVICE HIDE_SOL
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#define HIDE_ALL_ME_DEVICE (HIDE_MEI1|HIDE_MEI2|HIDE_MEI3|HIDE_MEI4|HIDE_AMT_DEVICE)
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#define HIDE_SPS_DEVICE (HIDE_MEI3|HIDE_MEI4|HIDE_AMT_DEVICE)
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/**
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Abstract MEI message allowance in non MeNormalBiosPath definition
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Bit0 - IMR and DID messages are allowed to be sent with this BIOS path
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Bit1 - EOP message is allowed to be sent with this BIOS path
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Bit2 - HMRFPO DISABLE message is allowed to be sent with this BIOS path
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Bit3 - SET ME ENABLE message is allowed to be sent with this BIOS path
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Bit4 - GLOBAL RESET message is allowed to be sent with this BIOS path
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BIT5 - HMRFPO messages are allowed to be sent with this ME Bios boot path
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BIT6 - GEN messages are allowed to be sent with this ME Bios boot path
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BIT7 - MEI BUS messages are allowed to be sent with this ME Bios boot path
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BIT9 - All MKHI messages except for MCA Group are allowed to be sent with this ME Bios boot path
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BIT8 - Messages that for dynamic ME addressN are allowed to be sent with this ME Bios boot path
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BIT10 - READ FROM MPHY and SET EDEBUG STATE messages are allowed to be sent with this BIOS path
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BIT11 - CORE BIOS DONE message is allowed to be sent with this BIOS path
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BIT12 - Measurement message is allowed to be sent with this BIOS path
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BIT13 - GET IP FIRMWARE message is allowed to be sent with this BIOS path
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BIT14 - TERMINATE HECI message is allowed to be sent with this BIOS path
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BIT15 - GET BIOS SEED message is allowed to be sent with this BIOS path
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BIT31 - All messages are allowed to be sent with this ME Bios boot path
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**/
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typedef UINT32 MESSAGE_ALLOWANCE;
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#define IMR_AND_DID_MSG_ALLOWANCE BIT0
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#define EOP_MSG_ALLOWANCE BIT1
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#define HMRFPO_DISABLE_MSG_ALLOWANCE BIT2
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#define SET_ME_ENABLE_MSG_ALLOWANCE BIT3
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#define GLOBAL_RST_MSG_ALLOWANCE BIT4
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#define HMRFPO_GRP_MSG_ALLOWANCE BIT5
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#define GEN_GRP_MSG_ALLOWANCE BIT6
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#define MEI_BUS_MSG_ALLOWANCE BIT7
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#define DYN_CLIENT_MSG_ALLOWANCE BIT8
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#define MKHI_MSG_ALLOWANCE BIT9
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#define E_DEBUG_MODE_MSG_ALLOWANCE BIT10
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#define CORE_BIOS_DONE_ALLOWANCE BIT11
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#define MEASUREMENT_MSG_ALLOWANCE BIT12
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#define GET_IP_FIRMWARE_MSG_ALLOWANCE BIT13
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#define TERMINATE_HECI_MSG_ALLOWANCE BIT14
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#define BIOS_SEED_ALLOWANCE BIT15
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#define ALL_MSG_ALLOWANCE BIT31
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//
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// Prototypes
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//
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/**
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Checks ME Boot path. The function provides ME BIOS boot path based on current
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HECI1 FW Status Register. HECI1 must be enabled before invoking the function.
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The FW registers may report multiple statuses to reflect Me Bios boot path,
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BIOS will follow the prioritized Me Bios boot path to continue boot.
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If the priority changes, then BOOT_PATH enumerated type shall be
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adjusted as well to reflect the actual priority.
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@retval ME_BIOS_BOOT_PATH Me-Bios Path taken based on FWSTS registers
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@see ME_BIOS_BOOT_PATH - for available paths
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**/
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ME_BIOS_BOOT_PATH
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CheckMeBootPath (
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VOID
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);
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/**
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Returns the mapping of CSME devices that need to be hidden.
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The mapping is based only on ME-Bios boot path taken. Additional devices
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might be hidden later based on other platform policies.
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@retval ME_DEV_EXPOSURE Mapping of CSME devices to be hidden
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@see ME_DEV_EXPOSURE for bit assignment
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**/
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ME_DEV_EXPOSURE
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GetBootPathMeDevHidePolicy (
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VOID
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);
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/**
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Determines if the HECI device is present.
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If present, initializes it to be used by the BIOS.
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@param[in] HeciDev The HECI device to be accessed.
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@retval EFI_SUCCESS The function completed successfully.
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@retval EFI_DEVICE_ERROR No HECI device
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@retval EFI_TIMEOUT HECI does not return the buffer before timeout
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@retval EFI_UNSUPPORTED HECI MSG is unsupported
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**/
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EFI_STATUS
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EFIAPI
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SmmHeciInitialize (
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IN HECI_DEVICE HeciDev
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);
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/**
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Heci Re-initialization for Host
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@param[in] HeciDev The HECI device to be accessed.
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@retval EFI_SUCCESS Heci Re-initialization successful
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@retval EFI_TIMEOUT ME is not ready
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@retval EFI_DEVICE_ERROR Failed to initialize HECI
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**/
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EFI_STATUS
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EFIAPI
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SmmHeciReInitialize (
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IN HECI_DEVICE HeciDev
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);
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/**
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Reads a message from CSME through HECI.
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@param[in] HeciDev The HECI device to be accessed.
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@param[in] Blocking Used to determine if the read is BLOCKING or NON_BLOCKING.
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@param[in, out] MessageBody Pointer to a buffer used to receive a message.
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@param[in, out] Length Pointer to the length of the buffer on input and the length
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of the message on return. (in bytes)
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@retval EFI_SUCCESS One message packet read.
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@retval EFI_DEVICE_ERROR Failed to initialize HECI
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@retval EFI_NOT_READY HECI is not ready for communication
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@retval EFI_TIMEOUT Failed to receive a full message on time
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@retval EFI_NO_RESPONSE No response from CSME
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@retval EFI_BUFFER_TOO_SMALL The caller's buffer was not large enough
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@retval EFI_UNSUPPORTED Current ME mode doesn't support this message through this HECI
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**/
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EFI_STATUS
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EFIAPI
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SmmHeciReceive (
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IN HECI_DEVICE HeciDev,
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IN UINT32 Blocking,
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IN OUT UINT32 *MessageBody,
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IN OUT UINT32 *Length
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);
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/**
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Function sends one message (of any length) through the HECI circular buffer.
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@param[in] HeciDev The HECI device to be accessed.
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@param[in] Message Pointer to the message data to be sent.
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@param[in] Length Length of the message in bytes.
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@param[in] HostAddress The address of the host processor.
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@param[in] MeAddress Address of the ME subsystem the message is being sent to.
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@retval EFI_SUCCESS One message packet sent.
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@retval EFI_DEVICE_ERROR Failed to initialize HECI
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@retval EFI_NOT_READY HECI is not ready for communication
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@retval EFI_TIMEOUT CSME failed to empty the circular buffer
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@retval EFI_UNSUPPORTED Current ME mode doesn't support send this message through this HECI
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**/
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EFI_STATUS
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EFIAPI
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SmmHeciSend (
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IN HECI_DEVICE HeciDev,
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IN UINT32 *Message,
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IN UINT32 Length,
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IN UINT8 HostAddress,
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IN UINT8 MeAddress
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);
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/**
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Function sends one message through the HECI circular buffer and waits
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for the corresponding ACK message.
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@param[in] HeciDev The HECI device to be accessed.
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@param[in][out] Message Pointer to the message buffer.
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@param[in] Length Length of the message in bytes.
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@param[in][out] RecLength Length of the message response in bytes.
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@param[in] HostAddress Address of the sending entity.
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@param[in] MeAddress Address of the ME entity that should receive the message.
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@retval EFI_SUCCESS Command succeeded
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@retval EFI_DEVICE_ERROR Failed to initialize HECI
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@retval EFI_NOT_READY HECI is not ready for communication
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@retval EFI_TIMEOUT CSME failed to empty or fill the circular buffer
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@retval EFI_UNSUPPORTED Current ME mode doesn't support send this message through this HECI
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**/
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EFI_STATUS
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EFIAPI
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SmmHeciSendwAck (
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IN HECI_DEVICE HeciDev,
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IN OUT UINT32 *Message,
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IN UINT32 Length,
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IN OUT UINT32 *RecLength,
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IN UINT8 HostAddress,
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IN UINT8 MeAddress
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);
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/**
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Me reset and waiting for ready
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@param[in] HeciDev The HECI device to be accessed.
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@param[in] Delay The biggest waiting time
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@retval EFI_SUCCESS Host Ready bit cleared
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@retval EFI_TIMEOUT Host Ready bit not cleared
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@retval EFI_DEVICE_ERROR Failed to initialize HECI
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**/
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EFI_STATUS
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EFIAPI
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SmmMeResetWait (
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IN HECI_DEVICE HeciDev,
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IN UINT32 Delay
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);
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/**
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Function forces a reinit of the heci interface by following the reset heci interface via host algorithm
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in HPS section 4.1.1.1
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@param[in] HeciDev The HECI device to be accessed.
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@retval EFI_SUCCESS Interface reset successful
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@retval EFI_TIMEOUT ME is not ready
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**/
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EFI_STATUS
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EFIAPI
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SmmResetHeciInterface (
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IN HECI_DEVICE HeciDev
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);
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/**
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Get an abstract Intel HECI1 State from Firmware Status Register.
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This is used to control BIOS flow for different Intel ME functions.
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@param[out] MeStatus Pointer for status report
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@see MeState.h - Abstract ME status definitions.
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@retval EFI_SUCCESS MeStatus copied
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@retval EFI_INVALID_PARAMETER Pointer to MeStatus is invalid
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@retval EFI_NOT_FOUND HECI1 Device hidden
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**/
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EFI_STATUS
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EFIAPI
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SmmHeciGetMeStatus (
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OUT UINT32 *MeStatus
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);
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/**
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Get HECI1 Mode
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@param[out] MeMode Pointer for HECI1 Mode report
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@see MeState.h - Abstract ME Mode definitions.
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@retval EFI_SUCCESS MeMode copied
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@retval EFI_INVALID_PARAMETER Pointer to MeMode is invalid
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@retval EFI_NOT_FOUND HECI1 Device hidden
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**/
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EFI_STATUS
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EFIAPI
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SmmHeciGetMeMode (
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OUT UINT32 *MeMode
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);
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//
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// Prototype for ME Policy from PEI and DXE phase
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//
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/**
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Read the ME policy to see if HECI timeouts are enabled.
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@retval TRUE Timeout is enabled
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@retval FALSE Timeout is disabled
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**/
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extern
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BOOLEAN
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MeHeciTimeoutsEnabled (
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VOID
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);
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/**
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Read the ME policy to see if HECI message check is enabled for Bios Boot Path.
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@retval TRUE HECI message check is enabled
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@retval FALSE HECI message check is disabled
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**/
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BOOLEAN
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MeHeciMessageCheckEnabled (
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VOID
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);
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#endif // _SMM_HECI_LIB_H
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