191 lines
13 KiB
C
191 lines
13 KiB
C
/** @file
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This function offers an interface to dynamically modify GPIO table before memory initialization.
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;******************************************************************************
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;* Copyright (c) 2018, Insyde Software Corporation. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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#include <Library/PeiOemSvcChipsetLib.h>
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#include <Pins/GpioPinsVer2Lp.h>
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#include <Library/GpioLib.h>
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#include <PlatformGpioConfig.h>
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static GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTablePreMemTglUDdr4_ProjectBoard[] =
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{
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{0x0}
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};
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//[start-210731-STORM1101-modify]//
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#ifdef C770_SUPPORT
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//[-start-210908-YUNLEI0131-modify]//
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static GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG YogaC770_DGPU_GPIOTable[] =
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{
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{GPIO_VER2_LP_GPP_A15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}}, // PEG_RST_M_N
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{GPIO_VER2_LP_GPP_A20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermNone , GpioPadConfigUnlock }}, // GPU_PCIE_WAKE_N
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{GPIO_VER2_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioPadLock}},//GPU_CLKREQ3_N
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{GPIO_VER2_LP_GPP_E10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, // DGPU_PWR_CTRL_EN
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{GPIO_VER2_LP_GPP_F15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//Board ID12
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{GPIO_VER2_LP_GPP_F16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}}, //Board ID13
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};
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//[-end-210908-YUNLEI0131-modify]//
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static GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG YogaC770_14or16BoardID_GPIOTable[] =
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{
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{GPIO_VER2_LP_GPP_R6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//Board ID5
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{GPIO_VER2_LP_GPP_R7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//Board ID6
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};
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#endif
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//[end-210731-STORM1101-modify]//
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static GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTablePreMemTglUDdr4Simics_ProjectBoard[] =
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{
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{GPIO_VER2_LP_GPP_C11, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WWAN_FCP_OFF_N
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{GPIO_VER2_LP_GPP_D15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WWAN_DISABLE_N
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{GPIO_VER2_LP_GPP_H23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WWAN_PWREN
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{GPIO_VER2_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WWAN_PERST_N
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// {GPIO_VER2_LP_GPP_C9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //WWAN_WAKE_N
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{GPIO_VER2_LP_GPP_C10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WWAN_RST_N
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{0x0}
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};
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static GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTableTglUDdr4WwanOnEarlyPreMem_ProjectBoard[] =
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{
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{GPIO_VER2_LP_GPP_H23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_PWREN
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{GPIO_VER2_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_FCP_OFF_N
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{GPIO_VER2_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_RST_N
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{GPIO_VER2_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_PERST_N
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{GPIO_VER2_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock}}, //WWAN_WAKE_N
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{GPIO_VER2_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_DISABLE_N
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};
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static GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTableTglUDdr4WwanOffEarlyPreMem_ProjectBoard[] =
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{
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{GPIO_VER2_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_RST_N
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{GPIO_VER2_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_PERST_N
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{GPIO_VER2_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_FCP_OFF_N
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};
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#ifdef S570_SUPPORT
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//[-start-210917-QINGLIN0068-modify]//
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GPIO_INIT_CONFIG S570_DGPU_GPIOTable[] = {
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// ====================================================================================================================================================================================================
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// DGPU GPIIO init
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// ====================================================================================================================================================================================================
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{GPIO_VER2_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioPadLock}},//GPU_CLKREQ_N
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// {GPIO_VER2_LP_GPP_D14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//GPU_EVENT_N
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// {GPIO_VER2_LP_GPP_B8, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//FB_GC6_EN_R
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{GPIO_VER2_LP_GPP_D0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//PXS_RST_N_R
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{GPIO_VER2_LP_GPP_B7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//PXS_PWREN
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// {GPIO_VER2_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//NVVDD_PWROK_R
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{GPIO_VER2_LP_GPP_H9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//VGA_PWRGD
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{GPIO_VER2_LP_GPP_F15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//Board ID12
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{GPIO_VER2_LP_GPP_F16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}} //Board ID13
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};
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//[-end-210917-QINGLIN0068-modify]//
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#endif
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//[-start-210803-QINGLIN0008-add]//
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//[-start-210908-QINGLIN0055-modify]//
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//[-start-210914-SHAONN0007-modify]//
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#ifdef S370_SUPPORT
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static GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG S370_DGPU_GPIOTable[] =
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{
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{GPIO_VER2_LP_GPP_F15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}}, //Board ID12
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{GPIO_VER2_LP_GPP_F16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}}, //Board ID13
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{GPIO_VER2_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioPadLock}},//GPU_CLKREQ3_N
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{GPIO_VER2_LP_GPP_A15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//PEG_RST_N
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{GPIO_VER2_LP_GPP_A20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermNone , GpioPadConfigUnlock }}, //GPU_PCIE_WAKE_N
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{GPIO_VER2_LP_GPP_D14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//VGA_CORE_SAMC_SA_VR_PG_R2
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{GPIO_VER2_LP_GPP_E10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, // DGPU_PWR_CTRL_EN
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};
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//[-end-210914-SHAONN0007-modify]//
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//[-end-210908-QINGLIN0055-modify]//
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#endif
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//[-end-210803-QINGLIN0008-add]//
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//[-start-210831-GEORGE0001-add]//
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#if defined(S77014_SUPPORT) || defined(S77014IAH_SUPPORT)
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static GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG S77014_DGPU_GPIOTable[] =
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{
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{GPIO_VER2_LP_GPP_E11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioOutputStateUnlock}},//PXS_PWREN
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{GPIO_VER2_LP_GPP_D18, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioLockDefault}},//VGA_PWRGD
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{GPIO_VER2_LP_GPP_H13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioOutputStateUnlock}},//PXS_RST_R_N
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{GPIO_VER2_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioPadLock}},//GPU_CLKREQ_N
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{GPIO_VER2_LP_GPP_F15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//Board ID12
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{GPIO_VER2_LP_GPP_F16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioLockDefault}},//Board ID13
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};
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#endif
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//[-end-210831-GEORGE0001-add]//
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/**
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This function offers an interface to dynamically modify GPIO table before memory initialization.
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@param[in, out] GpioTablePreMem On entry, points to a structure that specifies the GPIO setting.
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On exit, points to the updated structure.
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@param[in, out] GpioTableCountPreMem On entry, points to a value that the length of GPIO table .
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On exit, points to the updated value.
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@retval EFI_UNSUPPORTED Returns unsupported by default.
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@retval EFI_MEDIA_CHANGED Alter the Configuration Parameter.
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@retval EFI_SUCCESS The function performs the same operation as caller.
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The caller will skip the specified behavior and assuming
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that it has been handled completely by this function.
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*/
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EFI_STATUS
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OemSvcModifyGpioSettingTablePreMem (
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IN OUT GPIO_INIT_CONFIG **GpioTablePreMem,
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IN OUT UINT16 *GpioTableCountPreMem
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)
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{
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/*++
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Todo:
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Add project specific code in here.
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--*/
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//
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// *GpioTablePreMem = mGpioTablePreMemTglUDdr4Simics;
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//
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// *GpioTableCountPreMem = 5;
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//[-start-210721-QINGLIN0001-modify]//
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#ifdef LCFC_SUPPORT
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#if defined (S570_SUPPORT)
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*GpioTablePreMem = S570_DGPU_GPIOTable;
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*GpioTableCountPreMem = sizeof(S570_DGPU_GPIOTable)/sizeof(GPIO_INIT_CONFIG);
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return EFI_MEDIA_CHANGED;
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//[start-210731-STORM1101-modify]//
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#elif defined(C770_SUPPORT)
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// storm_bringup can optimise here
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*GpioTablePreMem = YogaC770_DGPU_GPIOTable;
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*GpioTableCountPreMem = sizeof(YogaC770_DGPU_GPIOTable)/sizeof(GPIO_INIT_CONFIG);
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return EFI_MEDIA_CHANGED;
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//[end-210731-STORM1101-modify]//
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//[-start-210803-QINGLIN0008-add]//
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#elif defined(S370_SUPPORT)
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*GpioTablePreMem = S370_DGPU_GPIOTable;
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*GpioTableCountPreMem = sizeof(S370_DGPU_GPIOTable)/sizeof(GPIO_INIT_CONFIG);
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return EFI_MEDIA_CHANGED;
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//[-end-210803-QINGLIN0008-add]//
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//[-start-210831-GEORGE0001-add]//
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#elif defined(S77014_SUPPORT) || defined(S77014IAH_SUPPORT)
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*GpioTablePreMem = S77014_DGPU_GPIOTable;
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*GpioTableCountPreMem = sizeof(S77014_DGPU_GPIOTable)/sizeof(GPIO_INIT_CONFIG);
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return EFI_MEDIA_CHANGED;
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//[-end-210831-GEORGE0001-add]//
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#else
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return EFI_UNSUPPORTED;
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#endif
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#else
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return EFI_UNSUPPORTED;
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#endif
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//[-end-210721-QINGLIN0001-modify]//
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}
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