99 lines
5.9 KiB
C
99 lines
5.9 KiB
C
/** @file
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;******************************************************************************
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;* Copyright (c) 2021, Insyde Software Corporation. All Rights Reserved.
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;*
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;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
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;* transmit, broadcast, present, recite, release, license or otherwise exploit
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;* any part of this publication in any form, by any means, without the prior
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;* written permission of Insyde Software Corporation.
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;*
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;******************************************************************************
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*/
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// xHC Latency Tolerance Parameters used during initialization process
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#define V_XHCI_LTR_HIT_1 0x033200A3
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#define V_XHCI_LTR_HIT_2 0x00050001
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#define V_XHCI_LTR_MIT_1 0x00CB0028
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#define V_XHCI_LTR_MIT_2 0x00050001
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#define V_XHCI_LTR_LIT_1 0x00CB001E
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#define V_XHCI_LTR_LIT_2 0x00050001
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// xHCI controller DID for USB IP Version detection
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// xHCI Controler IDs with USB IP V16_0
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#define V_XHCI_DID_CNP_LP 0x9DED
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#define V_XHCI_DID_CNP_H 0xA36D
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// xHCI Controler IDs with USB IP V17_0
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#define V_XHCI_DID_CPU_V17_0_1 0x8A13
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// xHCI Controler IDs with USB IP V17_1
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#define V_XHCI_DID_PCH_V17_1_1 0x34ED
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#define V_XHCI_DID_PCH_V17_1_2 0x38ED
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#define V_XHCI_DID_PCH_V17_1_3 0x3DED
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// USB IP Version enumeration
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typedef enum {
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V16_0 = 0,
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V17_0,
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V17_1
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} USB_IP_VERSION;
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// xHCI controller information structure
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typedef struct {
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BOOLEAN OnSouth;
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USB_IP_VERSION IpVersion; // Version of USB IP (value according to USB_IP_VERSION enumeration
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BOOLEAN IsCpuStepA0; // Flag for applying programming in specific steps for CPU
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UINT16 DeviceId; // Host Controller device ID
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UINT32 UsbLtrHigh; // High Idle Time Control LTR parameters
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UINT32 UsbLtrMid; // Medium Idle Time Control LTR parameters
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UINT32 UsbLtrLow; // Low Idle Time Control LTR parameters
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} USB_CONTROLLER_INFO;
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//RC2117 remove this define from UsbRegs.h and it will cause ddt build error
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#define R_XHCI_CFG_MSI_NEXT 0x81
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#define V_XHCI_MEM_HCIVERSION_0110 0x0110
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#define B_XHCI_MEM_HCSPARAMS3_U1DEL 0x000000FF
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#define R_XHCI_MEM_HCCPARAMS1 0x10
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#define R_XHCI_MEM_XECP_CMDM_CTRL_REG1 0x818C ///< Command Manager Control 1
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#define B_XHCI_MEM_PMCTRL_SSU3LFPS_DET 0xFF00 ///< SS U3 LFPS Detection Threshold Mask
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#define N_XHCI_MEM_PMCTRL_SSU3LPFS_DET 8 ///< SS U3 LFPS Detection Threshold position
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#define R_XHCI_MEM_AUX_CTRL_REG1 0x80E0
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#define R_XHCI_MEM_USB2_LINK_MGR_CTRL_REG1_DW1 0x80F0 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
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#define R_XHCI_MEM_USB2_LINK_MGR_CTRL_REG1_DW4 0x80FC ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4
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#define R_XHCI_MEM_HOST_CTRL_BW_CTRL_REG 0x8100 ///< HOST_CTRL_BW_CTRL_REG - Host Controller Bandwidth Control Register
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#define R_XHCI_MEM_HOST_CTRL_TRM_REG2 0x8110 ///< HOST_CTRL_TRM_REG2 - Host Controller Transfer Manager Control 2
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#define R_XHCI_MEM_HOST_CTRL_BW_MAX_REG 0x8128 ///< HOST_CTRL_BW_MAX_REG - Max BW Control Reg 4
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#define B_XHCI_MEM_HOST_CTRL_BW_MAX_REG_MAX_HS_BW 0xFFF000 ///< HOST_CTRL_BW_MAX_REG - Max. Number of BW units for HS ports
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#define N_XHCI_MEM_HOST_CTRL_BW_MAX_REG_MAX_HS_BW 12 ///< HOST_CTRL_BW_MAX_REG - Max. Number of BW units for HS ports position
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#define R_XHCI_MEM_AUXCLKCTL 0x816C ///< xHCI Aux Clock Control Register
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#define B_XHCI_MEM_HOST_BW_OV_HS_REG_OVHD_HSTTBW 0x0FFF ///< Mask for Overhead per packet for HS-TT BW calculations value
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#define B_XHCI_MEM_HOST_BW_OV_HS_REG_OVHD_HSBW 0xFFF000 ///< Mask for Overhead per packet for HS BW calculations value
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#define N_XHCI_MEM_HOST_BW_OV_HS_REG_OVHD_HSBW 12
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#define R_XHCI_MEM_HOST_BW_OV_HS_REG 0x80C8 ///< HOST_BW_OV_HS_REG - High Speed TT Bandwidth Overhead
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#define R_XHCI_MEM_THROTT 0x819C ///< XHCI Throttle Control
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#define R_XHCI_MEM_THROTT2 0x81B4 ///< XHCI Throttle
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#define N_XHCI_MEM_D0I2CTRL_MSI_IDLE_THRESHOLD 4 ///< Bitshift for MSI Idle Threshold
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#define R_XHCI_MEM_TRBPRFCTRLREG1 0x81D0 ///< TRB Prefetch Control Register 1
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#define R_XHCI_MEM_TRBPRFCACHEINVREG 0x81D8 ///< TRB Prefetch Cache Invalidation Register 1
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#define N_XHCI_MEM_TRBPRFCACHEINVREG_EN_TRB_FLUSH 17 ///< Enable TRB flushing for various command
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#define R_XHCI_MEM_ENH_CLK_GATE_CTRL 0x83D8 ///< Enhanced Clock Gate Control Policy Register
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#define R_XHCI_MEM_HOST_CTRL_SSP_LFPS_REG2 0x8E74
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#define R_XHCI_MEM_HOST_CTRL_SSP_LFPS_REG3 0x8E78
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#define R_XHCI_MEM_HOST_CTRL_SSP_CONFIG_REG1 0x8E80
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#define B_XHCI_MEM_CAPABILITY_ID 0xFF ///< Capability ID
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#define V_XHCI_MEM_DBC_DCID 0x0A ///< Debug Capability ID
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#define R_XHCI_MEM_DBC_DCCTRL 0x20 ///< Debug Capability Control Register (DCCTRL)
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#define B_XHCI_MEM_DBC_DCCTRL_DCR BIT0 ///< Debug Capability - DbC Run (DCR)
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#define R_XHCI_MEM_DBC_DCST 0x24 ///< Debug Capability Status Register (DCST)
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#define N_XHCI_MEM_DBC_DCST_DBG_PORT_NUMBER 24 ///< Debug Port Number Offset in DCST register
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#define B_XHCI_MEM_CAPABILITY_NEXT_CAP_PTR 0xFF00 ///< Next Capability Pointer
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#define N_XHCI_MEM_CAPABILITY_NEXT_CAP_PTR 8 ///< Byte shift for next capability pointer
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#define B_XHCI_MEM_PORTSCXUSB3_PED BIT1 ///< Port Enable/Disabled
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#define B_XHCI_MEM_PORTSCXUSB3_WPR BIT31 ///< Warm Port Reset
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