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alder_lake_bios/Intel/AlderLake/AlderLakeFspPkg/AlderLakeFspPkg.fdf

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## @file
#
#******************************************************************************
#* Copyright 2021 Insyde Software Corp. All Rights Reserved.
#*
#* You may not reproduce, distribute, publish, display, perform, modify, adapt,
#* transmit, broadcast, present, recite, release, license or otherwise exploit
#* any part of this publication in any form, by any means, without the prior
#* written permission of Insyde Software Corp.
#*
#******************************************************************************
## @file
# FDF file of Platform.
#
# @copyright
# INTEL CONFIDENTIAL
# Copyright 2016 - 2021 Intel Corporation.
#
# The source code contained or described herein and all documents related to the
# source code ("Material") are owned by Intel Corporation or its suppliers or
# licensors. Title to the Material remains with Intel Corporation or its suppliers
# and licensors. The Material may contain trade secrets and proprietary and
# confidential information of Intel Corporation and its suppliers and licensors,
# and is protected by worldwide copyright and trade secret laws and treaty
# provisions. No part of the Material may be used, copied, reproduced, modified,
# published, uploaded, posted, transmitted, distributed, or disclosed in any way
# without Intel's prior express written permission.
#
# No license under any patent, copyright, trade secret or other intellectual
# property right is granted to or conferred upon you by disclosure or delivery
# of the Materials, either expressly, by implication, inducement, estoppel or
# otherwise. Any license under such intellectual property rights must be
# express and approved by Intel in writing.
#
# Unless otherwise agreed by Intel in writing, you may not remove or alter
# this notice or any other notice embedded in Materials by Intel or
# Intel's suppliers or licensors in any way.
#
# This file contains an 'Intel Peripheral Driver' and is uniquely identified as
# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
# the terms of your license agreement with Intel or your vendor. This file may
# be modified by the user, subject to additional terms of the license agreement.
#
# @par Specification
##
[Defines]
# Initialize base address of first component of FSP
DEFINE FLASH_BASE = 0xFFE00000 # @todo set reasonable Flash Base once FSP size is settled
DEFINE FLASH_BLOCK_SIZE = 0x00001000 #The block size
!if ("GCC" in $(FAMILY))
#
# Flash Size for GCC
#
!if $(TARGET) == "RELEASE"
#============================================================================#
DEFINE FLASH_SIZE = 0x0013F000 #The flash size in bytes of the FSP #
DEFINE FLASH_NUM_BLOCKS = 0x13F #The number of blocks #
#============================================================================#
#============================================================================#
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFsptSize = 0x00010000 #
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspmSize = 0x000C0000 #
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspsSize = 0x0006F000 #
#============================================================================#
!else
#============================================================================#
DEFINE FLASH_SIZE = 0x0020F000 #The flash size in bytes of the FSP #
DEFINE FLASH_NUM_BLOCKS = 0x20F #The number of blocks #
#============================================================================#
#============================================================================#
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFsptSize = 0x00010000 #
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspmSize = 0x00160000 #
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspsSize = 0x0009F000 #
#============================================================================#
!endif
!endif
!if ("MSFT" in $(FAMILY)) || ($(TOOL_CHAIN_TAG) == "CLANGPDB")
#
# Flash Size for Visual Studio
#
!if $(TARGET) == "RELEASE"
#============================================================================#
DEFINE FLASH_SIZE = 0x0012F000 #The flash size in bytes of the FSP #
DEFINE FLASH_NUM_BLOCKS = 0x12F #The number of blocks #
#============================================================================#
#============================================================================#
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFsptSize = 0x00010000 #
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspmSize = 0x000B0000 #
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspsSize = 0x0006F000 #
#============================================================================#
!else
#============================================================================#
DEFINE FLASH_SIZE = 0x001FF000 #The flash size in bytes of the FSP #
DEFINE FLASH_NUM_BLOCKS = 0x1FF #The number of blocks #
#============================================================================#
#============================================================================#
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFsptSize = 0x00010000 #
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspmSize = 0x00140000 #
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspsSize = 0x000AF000 #
#============================================================================#
!endif
!endif
################################################################################
#
# FD Section
# The [FD] Section is made up of the definition statements and a
# description of what goes into the Flash Device Image. Each FD section
# defines one flash "device" image. A flash device image may be one of
# the following: Removable media bootable image (like a boot floppy
# image,) an Option ROM image (that would be "flashed" into an add-in
# card,) a System "Flash" image (that would be burned into a system's
# flash) or an Update ("Capsule") image that will be used to update and
# existing system flash.
#
################################################################################
[FD.FSP]
BaseAddress = $(FLASH_BASE) | gIntelFsp2PkgTokenSpaceGuid.PcdFspAreaBaseAddress
Size = $(FLASH_SIZE) | gIntelFsp2PkgTokenSpaceGuid.PcdFspAreaSize
ErasePolarity = 1
BlockSize = $(FLASH_BLOCK_SIZE)
NumBlocks = $(FLASH_NUM_BLOCKS) #The number of blocks for 2Mb FLASH Device.
SET gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspBase = $(FLASH_BASE)
SET gIntelFsp2PkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase = $(FLASH_BASE) + $(gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspsSize)
#FSP-S
#FSP-S FV offset|FSP-S FV size
0x00000000|gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspsSize
gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspsBase|gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspsSize
FV = FSP-S
#FSP-M
#FSP-M FV offset = FSP-S size|FSP-M FV size
$(gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspsSize)|gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspmSize
gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspmBase|gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspmSize
FV = FSP-M
#FSP-T
#FSP-T FV offset = FSP-S size + FSP-M size|FSP-T FV size
$(gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspsSize) + $(gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFspmSize)|gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFsptSize
gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFsptBase|gAlderLakeFspPkgTokenSpaceGuid.PcdFlashFvFsptSize
FV = FSP-T
################################################################################
#
# FV Section
#
# [FV] section is used to define what components or modules are placed within a flash
# device file. This section also defines order the components and modules are positioned
# within the image. The [FV] section consists of define statements, set statements and
# module statements.
#
################################################################################
[FV.FSP-T]
BlockSize = 0x00001000
FvAlignment = 16 #FV alignment and FV attributes setting.
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
FvNameGuid = 7BEBD21A-A1E5-4C4C-9CA1-A0C168BCBD9D
#
# FSP header
#
INF RuleOverride = FSPHEADER $(FSP_PACKAGE)/FspHeader/FspHeader.inf
INF RuleOverride = RELOC IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
#
# Project specific configuration data files
#
!if gAlderLakeFspPkgTokenSpaceGuid.PcdCfgRebuild == FALSE
FILE RAW = $(FSP_T_UPD_FFS_GUID) {
SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/$(FSP_T_UPD_TOOL_GUID).bin
}
!endif
[FV.FSP-M]
BlockSize = 0x00001000
FvAlignment = 16 #FV alignment and FV attributes setting.
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
FvNameGuid = 52F1AFB6-78A6-448f-8274-F370549AC5D0
#
# FSP header
#
INF RuleOverride = FSPHEADER $(FSP_PACKAGE)/FspHeader/FspHeader.inf
#
# It is important to keep the proper order for these PEIMs
# for this implementation
#
INF RuleOverride = RELOC IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
#
# EDK2 master has removed PcdPeiCoreMaxPeimPerFv, PcdPeiCoreMaxFvSupported
# and PcdPeiCoreMaxPpiSupported.
# The override PeiMain is still using these PCDs, there will be build failure
# if it is used for edk2 master build. So here is to use non-override PeiMain
# for edk2 master build.
#
INF MdeModulePkg/Core/Pei/PeiMain.inf
INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
INF MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf
INF $(C1S_FSP_PATH)/FspGlobalDataInit/Pei/FspGlobalDataInitPei.inf
#[-start-180709-IB15590108-modify]#
!if $(FSP_DEBUG) == YES
INF $(C1S_FSP_PATH)/FspDebugInit/Pei/FspDebugServicePei.inf
!endif
#[-end-180709-IB15590108-modify]#
#
# Project specific PEIMs
#
INF $(C1S_FSP_PATH)/FspPcdInit/Pei/FspPcdInit.inf
#
# SiInit will produce a PPI for installing default policy PPI, so it has to be
# dispatch earlier.
#
INF $(C1S_PRODUCT_PATH)/SiInit/Pei/SiInitPreMemFsp.inf
INF $(C1S_FSP_PATH)/FspInit/Pei/FspInitPreMem.inf
#
# Description file
#
FILE RAW = D9093578-08EB-44DF-B9D8-D0C1D3D55D96 {
SECTION RAW = $(FSP_PACKAGE)/FspDescription/FspDescription.txt
}
#
# Project specific configuration data files
#
!if gAlderLakeFspPkgTokenSpaceGuid.PcdCfgRebuild == FALSE
FILE RAW = $(FSP_M_UPD_FFS_GUID) {
SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/$(FSP_M_UPD_TOOL_GUID).bin
}
!endif
[FV.FSP-S]
BlockSize = 0x00001000
FvAlignment = 16 #FV alignment and FV attributes setting.
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
FvNameGuid = 1B5C27FE-F01C-4fbc-AEAE-341B2E992A17
#
# FSP header
#
INF RuleOverride = FSPHEADER $(FSP_PACKAGE)/FspHeader/FspHeader.inf
#
# It is important to keep the proper order for these PEIMs
# for this implementation
#
INF RuleOverride = RELOC IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf
#
# Project specific configuration data files
#
!if gAlderLakeFspPkgTokenSpaceGuid.PcdCfgRebuild == FALSE
FILE RAW = $(FSP_S_UPD_FFS_GUID) {
SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/$(FSP_S_UPD_TOOL_GUID).bin
}
!endif
INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
#
# SiInit will produce a PPI for installing default policy PPI, so it has to be
# dispatch earlier.
#
INF RuleOverride = PE32 $(C1S_PRODUCT_PATH)/SiInit/Pei/SiInitFsp.inf
INF RuleOverride = PE32 $(C1S_FSP_PATH)/FspInit/Pei/FspInit.inf
#
# CpuMp PEIM for MpService PPI
#
INF RuleOverride = PE32 UefiCpuPkg/CpuMpPei/CpuMpPei.inf
INF RuleOverride = PE32 UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf
INF RuleOverride = PE32 $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitFsp.inf
INF RuleOverride = PE32 $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeFspTgl.inf
INF RuleOverride = PE32 $(PLATFORM_SI_PACKAGE)/IpBlock/Me/HeciInit/Dxe/HeciInitFsp.inf
INF RuleOverride = PE32 IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf
INF $(C1S_FSP_PATH)/FspInit/Pei/FspS3Notify.inf
!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
INF RuleOverride = PE32 MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf
FILE PEIM = 76ed893a-b2f9-4c7d-a05f-1ea170ecf6cd {
SECTION COMPRESS {
!if $(TARGET) == DEBUG
!if (gSiPkgTokenSpaceGuid.PcdAdlLpSupport == FALSE)
SECTION Align = Auto PE32 = $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/Graphics/IntelGraphicsPeim/Binaries/IntelGraphicsPeimDebug.efi
!else
SECTION Align = Auto PE32 = $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/Graphics/IntelGraphicsPeim/Binaries/IntelGraphicsPeimAdlPDebug.efi
!endif
!else
!if (gSiPkgTokenSpaceGuid.PcdAdlLpSupport == FALSE)
SECTION Align = Auto PE32 = $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/Graphics/IntelGraphicsPeim/Binaries/IntelGraphicsPeim.efi
!else
SECTION Align = Auto PE32 = $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/Graphics/IntelGraphicsPeim/Binaries/IntelGraphicsPeimAdlP.efi
!endif
!endif
SECTION PEI_DEPEX_EXP = {gEfiPeiStallPpiGuid AND gEnablePeiGraphicsPpiGuid}
SECTION UI = "IntelGraphicsPeim"
}
}
!endif #PcdPeiDisplayEnable
INF RuleOverride = PE32 $(C1S_FSP_PATH)/FspEndOfPei2/FspEndOfPei2Peim.inf
#
# X64 module for notify phase
#
INF $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeFsp.inf
INF $(PLATFORM_SI_PACKAGE)/IpBlock/Me/HeciInit/Dxe/HeciInitDxeFsp.inf
INF $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxeFsp.inf
[Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.SEC.RELOC]
FILE SEC = $(NAMED_GUID) {
TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.PEIM.NORELOC]
FILE PEIM = $(NAMED_GUID) RELOCS_STRIPPED {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.PEIM]
FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.PEIM.PE32]
FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
COMPRESS {
PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
}
[Rule.Common.USER_DEFINED.FSPHEADER]
FILE RAW = $(NAMED_GUID) {
RAW BIN |.acpi
}
[Rule.Common.DXE_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
COMPRESS {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
}
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