148 lines
6.0 KiB
Plaintext
148 lines
6.0 KiB
Plaintext
## @file
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# FSP description file initializes configuration (PCD) settings for this project.
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#
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# @copyright
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# INTEL CONFIDENTIAL
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# Copyright 2020 - 2021 Intel Corporation.
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#
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# The source code contained or described herein and all documents related to the
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# source code ("Material") are owned by Intel Corporation or its suppliers or
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# licensors. Title to the Material remains with Intel Corporation or its suppliers
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# and licensors. The Material may contain trade secrets and proprietary and
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# confidential information of Intel Corporation and its suppliers and licensors,
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# and is protected by worldwide copyright and trade secret laws and treaty
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# provisions. No part of the Material may be used, copied, reproduced, modified,
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# published, uploaded, posted, transmitted, distributed, or disclosed in any way
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# without Intel's prior express written permission.
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#
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# No license under any patent, copyright, trade secret or other intellectual
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# property right is granted to or conferred upon you by disclosure or delivery
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# of the Materials, either expressly, by implication, inducement, estoppel or
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# otherwise. Any license under such intellectual property rights must be
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# express and approved by Intel in writing.
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#
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# Unless otherwise agreed by Intel in writing, you may not remove or alter
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# this notice or any other notice embedded in Materials by Intel or
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# Intel's suppliers or licensors in any way.
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#
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# This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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# "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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# the terms of your license agreement with Intel or your vendor. This file may
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# be modified by the user, subject to additional terms of the license agreement.
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#
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# @par Specification
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##
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#
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# TRUE is ENABLE. FALSE is DISABLE.
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#
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#
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# BIOS build switches configuration
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#
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[PcdsFixedAtBuild]
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#
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# CPU
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#
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gSiPkgTokenSpaceGuid.PcdBtgTxtLegacyPkgEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
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#
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# SA
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#
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gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE
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#
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# ME
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#
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gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE
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gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE
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#
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# SI
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#
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gSiPkgTokenSpaceGuid.PcdThcEnable|FALSE
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gSiPkgTokenSpaceGuid.PcdFspBinaryEnable|TRUE
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# HybridStorageDevice
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gSiPkgTokenSpaceGuid.PcdHybridStorageSupport|TRUE
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#
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# Since PcdSimicsEnable has been removed and TGL run in Simics Environment currently,
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# so follow original setting which set PcdBdatEnable = FALSE in Simics Environment
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#
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gSiPkgTokenSpaceGuid.PcdFspImageIdString|0x245053464C444124 #$ADLFSP$
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gSiPkgTokenSpaceGuid.PcdFspVersionRevision|0x65
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gSiPkgTokenSpaceGuid.PcdFspVersionBuild|0x70
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gSiPkgTokenSpaceGuid.PcdFspVersionMinor|0x00
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gSiPkgTokenSpaceGuid.PcdStatusCodeFlags|0x32
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gSiPkgTokenSpaceGuid.PcdMultiPhaseSiInitNumberOfPhases|1
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gAlderLakeFspPkgTokenSpaceGuid.PcdMiniBiosEnable|FALSE
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gAlderLakeFspPkgTokenSpaceGuid.PcdCfgRebuild|FALSE
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gAlderLakeFspPkgTokenSpaceGuid.PcdFspPerformanceEnable|FALSE
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gAlderLakeFspPkgTokenSpaceGuid.PcdMonoStatusCode|FALSE
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#
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# Symbol in release build
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#
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gAlderLakeFspPkgTokenSpaceGuid.PcdSymbolInReleaseEnable|FALSE
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!if $(TARGET) == RELEASE
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!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x02
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!else
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0
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!endif
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!else
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gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
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!endif
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## Indicates if to shadow PEIM on S3 boot path after memory is ready.<BR><BR>
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# TRUE - Shadow PEIM on S3 boot path after memory is ready.<BR>
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# FALSE - Not shadow PEIM on S3 boot path after memory is ready.<BR>
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# @Prompt Shadow Peim On S3 Boot.
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gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
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# Temp solution to avoid halt in PeiVariable->GetVariable (PeiGetVariable)
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0xFFF80000
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x10000
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# Use to override gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize
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gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x80000
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gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
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gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00100000
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gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength|0x00500000
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gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00020000
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## Specifies the FSP Header Spec Version
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gIntelFsp2PkgTokenSpaceGuid.PcdFspHeaderSpecVersion|0x23
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# This defines how much space will be used for heap in FSP temporary memory
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# x % of FSP temporary memory will be used for heap
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# (100 - x) % of FSP temporary memory will be used for stack
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# 0 means FSP will share the same stack with bootloader
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# In this case PcdFspTemporaryRamSize is used for Heap
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gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage|0
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# This is a platform specific global pointer used by FSP
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gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
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# Override PcdFspMaxPatchEntry to match FspHeader.aslc
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gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry|0x02
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## Specifies the number of variable MTRRs reserved for OS use. The default number of
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# MTRRs reserved for OS use is 0.
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# @Prompt Number of reserved variable MTRRs.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x0
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## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
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# @Prompt Timeout for the BSP to detect all APs for the first time.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|10000
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[PcdsPatchableInModule]
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gSiPkgTokenSpaceGuid.PcdRegBarBaseAddress|0xFB000000
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#
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# This entry will be patched during the build process
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#
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gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x12345678
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[PcdsDynamicExDefault]
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#
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# Include FSP PCD settings.
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#
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!include $(FSP_PACKAGE)/FspPkgPcdShare.dsc
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gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr|0x0 |