106 lines
4.0 KiB
C
106 lines
4.0 KiB
C
/** @file
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This file is SampleCode of the library for Intel TBT PEI
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Platform Policy Update.
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@copyright
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INTEL CONFIDENTIAL
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Copyright 2017 - 2021 Intel Corporation.
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The source code contained or described herein and all documents related to the
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source code ("Material") are owned by Intel Corporation or its suppliers or
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licensors. Title to the Material remains with Intel Corporation or its suppliers
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and licensors. The Material may contain trade secrets and proprietary and
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confidential information of Intel Corporation and its suppliers and licensors,
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and is protected by worldwide copyright and trade secret laws and treaty
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provisions. No part of the Material may be used, copied, reproduced, modified,
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published, uploaded, posted, transmitted, distributed, or disclosed in any way
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without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual
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property right is granted to or conferred upon you by disclosure or delivery
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of the Materials, either expressly, by implication, inducement, estoppel or
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otherwise. Any license under such intellectual property rights must be
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express and approved by Intel in writing.
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Unless otherwise agreed by Intel in writing, you may not remove or alter
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this notice or any other notice embedded in Materials by Intel or
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Intel's suppliers or licensors in any way.
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This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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"Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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the terms of your license agreement with Intel or your vendor. This file may
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be modified by the user, subject to additional terms of the license agreement.
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@par Specification Reference:
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**/
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#include <Library/DebugLib.h>
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#include <Ppi/SiPolicy.h>
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#include <Library/FspCommonLib.h>
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#include <FspsUpd.h>
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#include <Library/ConfigBlockLib.h>
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#if FixedPcdGetBool(PcdITbtEnable) == 1
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#include <TcssDataHob.h>
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#include <PeiITbtConfig.h>
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#endif
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#include <Library/HobLib.h>
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#include <Library/PcdLib.h>
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#include <TcssInfo.h>
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#include <TcssPeiConfig.h>
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/**
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This function performs TBT PEI Policy update.
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@param[in] SiPolicy The SI Policy PPI instance
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@param[in] FspsUpd The pointer of FspsUpd
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@retval EFI_SUCCESS The function completed successfully
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**/
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EFI_STATUS
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EFIAPI
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FspUpdatePeiTbtPolicy (
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IN OUT SI_POLICY_PPI *SiPolicy,
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IN FSPS_UPD *FspsUpd
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)
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{
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#if FixedPcdGetBool(PcdITbtEnable) == 1
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EFI_STATUS Status;
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UINT8 Index;
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PEI_ITBT_CONFIG *PeiITbtConfig;
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TCSS_DATA_HOB *TcssHob;
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TcssHob = NULL;
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DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP FspUpdatePeiTbtPolicy\n"));
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Status = GetConfigBlock ((VOID *) SiPolicy, &gPeiITbtConfigGuid, (VOID *) &PeiITbtConfig);
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ASSERT_EFI_ERROR (Status);
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//
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// Get status of each iTBT PCIe RP is enabled or not from Tcss Hob.
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//
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TcssHob = (TCSS_DATA_HOB *) GetFirstGuidHob (&gTcssHobGuid);
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for (Index = 0; Index < MAX_ITBT_PCIE_PORT; Index ++) {
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PeiITbtConfig->ITbtRootPortConfig[Index].ITbtPcieRootPortEn = FspsUpd->FspsConfig.ITbtPcieRootPortEn[Index];
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//
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// Set/Clear ITBT Policy for ITbtPcieRootPortEn depending upon each iTBT PCIe RP is enabled or not.
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//
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if (TcssHob != NULL) {
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PeiITbtConfig->ITbtRootPortConfig[Index].ITbtPcieRootPortEn &= TcssHob->TcssData.ItbtPcieRpEn[Index];
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}
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}
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PeiITbtConfig->ITbtGenericConfig.ITbtForcePowerOnTimeoutInMs = FspsUpd->FspsConfig.ITbtForcePowerOnTimeoutInMs;
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for (Index = 0; Index < MAX_HOST_ITBT_DMA_NUMBER; Index ++) {
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PeiITbtConfig->ITbtDmaLtr[Index] = FspsUpd->FspsConfig.ITbtDmaLtr[Index];
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}
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PeiITbtConfig->ITbtGenericConfig.ITbtConnectTopologyTimeoutInMs = FspsUpd->FspsConfig.ITbtConnectTopologyTimeoutInMs;
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PeiITbtConfig->ITbtGenericConfig.ITbtPcieTunnelingForUsb4 = FspsUpd->FspsConfig.ITbtPcieTunnelingForUsb4;
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PeiITbtConfig->ITbtGenericConfig.Usb4CmMode = FspsUpd->FspsConfig.Usb4CmMode;
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#endif
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return EFI_SUCCESS;
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}
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